CMOS低壓降線性穩壓器之分析設計與實作

Analysis, Design and Implementation of CMOS Low Dropout Regulators

潘宣亦(Hsuan-I Pan)

指導教授 ： 陳秋麟

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2008年)

https://doi.org/10.6342/NTU.2008.02138

摘要

近年來，低壓降線性穩壓器(LDO)已廣泛地應用在較低功率的穩壓與電壓轉換上。相較於切換式電源供應器，LDO只需少量的外部元件，便可提供一精確的輸出電壓。此外，LDO還有雜訊低、暫態響應迅速、成本低與體積小等特點。因此，不論是在電池供電之可攜式電子系統的電源管理中，或是在切換式電源供應器的後級穩壓上，LDO都被普遍地使用。
一般的互補型金氧半(CMOS) LDO，是使用P型場效電晶體(PMOS)作為主要的功率單元。然而這種LDO所使用的傳統頻率補償方式，需要一容值範圍從1µF到數十微法拉不等的外部負載電容，且此負載電容寄生的等效串聯電阻(ESR)阻值需位於一特定的隧道狀範圍內，LDO系統方能維持穩定。但是外部負載電容會讓電路體積無法更為縮小，而其ESR亦限制了LDO效能的最佳化。除了這些缺點，傳統頻率補償方式還會無可避免地造成高頻的電源拒斥效能較低頻差。
本論文介紹了LDO的基本背景知識，並回顧討論文獻中各種效能提昇的方法，接著提出了三個使用不同頻率補償方式實作之LDO。根據所提出的頻率補償方式，前二個LDO可增加負載電容與其ESR的穩定範圍，而第三個LDO則可改善高頻的電源拒斥效能。
在這三個LDO當中，第一個LDO利用分離式結構之功率單元以達成所提出之新型頻率補償方式，且使用0.33μF之負載電容即可保持穩定。相較於使用傳統頻率補償方式的LDO，此LDO的負載電容與其ESR的穩定範圍較大。因此，負載電容可使用不同種類的電容，並可使用極低ESR的負載電容以達成更優異的暫態響應。
第二個LDO所使用的極點-零點對補償方式乃是由第一個LDO所使用的頻率補償方式衍生而來。除了分離式結構之功率單元，亦使用了多路徑結構的誤差放大器來實現所提出的頻率頻償方式。此LDO對負載電容值無特殊的限制，只要負載電容的ESR較負載電阻小，即可維持穩定電壓輸出。因此，此LDO不但可在不使用外部負載電容的情形下保持穩定，也提供了負載電容選擇上的彈性。使用者可依成本、體積及暫態漣波大小等考量來選擇適當的負載電容。
第三個LDO則利用了一頻率補償策略來提昇高頻的電源拒斥效能。此補償策略乃是利用串接多個輸出阻抗較小的增益級，將回路中所有內部電路的極點皆設計在高於單位增益頻率(UGF)的頻段。由於內部回授路徑沒有低頻的極點，高頻的電源拒斥效能不會衰減。用這項頻率補償策略所實現的LDO，在滿載的情形下，直流的電源拒斥效能可達-42dB，而其頻寬則可達1MHz，因此適合供電給對電源雜訊較為敏感的電路方塊。

關鍵字

互補型金氧半 ； 低壓降線性穩壓器 ； 穩定度 ； 頻率補償 ； 電源拒拆效能

並列摘要

In recent years, low dropout regulator (LDO) has been widely utilized as the voltage regulation and conversion stage for low power applications. Compare with a switch-mode power supply, an LDO provides an accurate output voltage with only a few off-chip components. Furthermore, an LDO features lower noises, faster transient response, less cost and smaller volume. These advantages make LDO a popular building block for the power management of battery-powered portable electronic systems and for post regulation of switch-mode power supplies.
Nevertheless, for a generic CMOS LDO which uses PMOS as the pass device using the conventional compensation scheme, an off-chip load capacitor ranges between 1µF to tens of micro farads is required and its parasitic equivalent series resistance (ESR) values must fall into a specific tunnel-like region to guarantee system stability of the LDO. The off-chip load capacitor hinders board size reduction and the ESR limits the optimization of LDO performance. Moreover, there is inevitable PSR degradation at high frequencies if the conventional compensation scheme is used.
In this dissertation, the basic background knowledge of LDO and several existing performance enhancement techniques in literature are discussed. After that, the proposed compensation schemes with three fabricated LDOs are presented. Based on the proposed compensation schemes, two of the LDOs are designed to relieve the stability requirement of load capacitor and its ESR, and the other LDO improves the high-frequency power supply rejection (PSR) performance.
Among the three fabricated LDOs, the first LDO uses a novel compensation scheme and a split-structured pass device such that the LDO is stable with a 0.33μF load capacitor. Furthermore, compared with the LDO using the conventional compensation scheme, it has larger stable range for the load capacitor and the ESR. Therefore, different types of capacitors can be used by the proposed LDO and the transient response of the LDO can be optimized by using a load capacitor with ultra low ESR.
As for the second LDO, the pole-zero pairs compensation scheme derived from the first LDO is used. In addition to the split-structured pass device, a multi-path error amplifier is employed to realize the compensation scheme. The LDO imposes no specific constraint on the load capacitor and only requires the ESR of the load capacitor less than the equivalent load resistance. As a result, the LDO provides the capacitor-free operation and the flexibility for load capacitor selection. Users can choose any suitable load capacitor for the consideration of cost, board size and transient ripples.
To enhance the PSR at high frequencies, a compensation strategy is proposed and verified by the third LDO. Realized by cascading gain stages with lower output impedance, the compensation strategy pushes all internal poles beyond the unity-gain frequency of the loop gain. Since there is no internal low-frequency pole, the PSR degradation at high frequencies is avoided. In this way, The LDO achieves -42dB PSR at DC and the PSR bandwidth is 1MHz at full load. The LDO is suitable for supplying the circuit blocks sensitive to the ripples of the supply rails.

並列關鍵字

CMOS ； low dropout regulator ； stability ； compensation ； power supply

參考文獻

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