經銅線傳輸之百億位元乙太網路系統時脈回復機架構設計與性能分析

Design of a Timing Recovery and Performance Analysis for 10GBASE-T Ethernet System

林楚耘(Chu-Yun Lin)

指導教授 ： 曹恆偉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.02152

摘要

本論文主要針對百億位元乙太網路系統（10GBASE-T Ethernet System, IEEE 802.3an），提出在non-loop timing操作方式下所需之符元時脈回復機，並針對時脈誤差偵測器和內插器架構，進行深入分析與探討；使用典型架構（單一數位鎖相迴路與數個延遲鎖定迴路混合使用），以及所提出基於平均取樣相位所設計之符元時脈回復機，達成10GBASE-T系統四對線同步之目標；此外設計一種可減少迴路延遲之符元時脈回復機，降低時脈回復機輸出時脈抖動，並增加系統回復較高類比數位轉換器取樣時脈誤差之能力。藉由適用於10GBASE-T系統之接收機，評估所回復時脈，對於通道等化機制及串音干擾消除效能影響，在模擬結果中可發現，本論文所提出之架構均符合系統所需最小決策點訊噪比，可確保達到10GBASE-T規格中對於位元錯誤率之要求。

關鍵字

百億位元乙太網路 ； 符元時脈回復機 ； 時脈誤差偵測器 ； 內插器 ； 迴路延遲

並列摘要

This thesis proposes a symbol timing recovery architecture using non-loop timing scheme for 10GBASE-T Ethernet System (IEEE 802.3an). The timing error detector and the interpolator architecture are discussed in this thesis. In order to achieve the four-pair synchronization in the 10GBASE-T Ethernet System, two symbol timing recovery architectures are presented, including conventional (a single digital phase-locked loop accompanies with multiple delay-locked loops) one and average sampling phase one. In addition, a symbol timing recovery with reduced loop delay is proposed. It is able to lower the jitter of the recovered symbol clock and recover larger sampling frequency offset at the analog-to-digital converter. The performance of these symbol timing recovery architectures is compared in terms of the decision point signal-to-noise ratio (dpSNR) of an existing software 10GBASE-T receiver architecture. Simulation results show that the proposed architectures can meet the requirement of minimum dpSNR and achieve the bit-error-rate specification in the standard.

並列關鍵字

10GBASE-T (IEEE 802.3an) Ethernet System ； Symbol Timing Recovery ； Non-Loop Timing ； Timing Error Detector ； Interpolator ； Loop Delay

參考文獻

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