數百億位元多通道時脈資料回復電路之設計與分析

Design and Analysis of Tens of Gb/s Multi-Channel Clock and Data Recovery Circuits

高健凱(Chien-Kai Kao)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.01077

摘要

近幾年來，有線傳輸技術持續以指數的方式成長。為了增加輸入輸出連結的傳輸量，我們可以增加連結中資料傳輸的速度。但是更高的傳輸速度可能會有更大的高頻衰減。為了要補償更大的高頻衰減，增加了等化器的設計難度。此外，要從帶有衰減的資料串流中時取出時脈，對時脈與資料回復電路來說也是一種挑戰。增加輸入輸出通道數目是增加總資料傳輸量的另一個方法。
本論文分成兩個部分。第一個部分介紹一個4X16 Gb/s 多通道時脈與資料回復電路。我們使用相位內差式的時脈與資料回復電路和數位控制電路來降低晶片
面積。使用一個次諧波注入的震盪器來產生低抖動的正交相位來給相位內差器使用。在我們的設計中使用了抖動容忍增加的技術。此電路實作於40-nm CMOS 製程。
第二部分描述一個2X25 Gb/s 雙通道時脈與資料回復電路。為了降低系統的功率消耗，我們的設計使用了電荷導向式邏輯電路。並提出一個振幅鎖定迴路來抑制電荷導向式邏輯電路的輸出振幅變異。根據模擬，這個振幅鎖定迴路能降低50% 在電荷導向式邏輯電路中輸出振幅的變異。同時，振幅鎖定迴路面積與功耗只占據整個系統中很少的一部份。此電路實作於40-nm CMOS 製程。

關鍵字

時脈資料回復電路 ； 多通道 ； 振幅鎖定迴路

並列摘要

Wireline communication keeps exponential growth in recent years. To increase thethroughput of I/O connection, we can increase the data rata of I/O connection. However, the higher data rate may suffer from more channel loss. This increases the design difficulty on equalizer to compensate large high frequency loss. Besides, it is also a challenge for clock and data recovery to extract clock from a lossy data stream. Alternatively, we can increase the I/O counts to raise total throughput.
This thesis consists of two parts. The first part introduces architecture of a 4X16 Gb/s multi-channel clock and data recovery. We use phase-interpolator-based CDR and digital-controlled circuits to save chip area. And, a sub-harmonic injection-locked oscillator to generate low jitter quadrature clocks for phase interpolator. Then, jitter-tolerance enhancement technique is applied in our design. This circuit is implemented in 40-nm CMOS Technology.
The second part describes a 2X25 Gb/s two-channel clock and data recovery. To lower down power consumption of the system, charge-steering logic circuit is adopted in our design. An amplitude-locked loop (ALL) is proposed to suppress the output amplitude variation of charge-steering logic circuit. According to simulation results, this ALL can reduce 50% of output amplitude variation of CSL circuit. Meanwhile, the area and power overhead of ALL compared to the whole system are low. This circuit is implemented in 40-nm CMOS Technology.

並列關鍵字

clock and data recovery ； CDR ； multi-channel ； ALL ； amplitude-locked loop

參考文獻

[1] B. Razavi, “Charge Steering: A Low-Power Design Paradigm,” IEEE Custom Integr. Circuits Conf., Sept. 2013, pp. 1-8.

[2] N. Kalantari and J. F. Buckwalter, “A Multichannel Serial Link Receiver With Dual-Loop Clock-and-Data Recovery and Channel Equalization,” IEEE Trans. Circuits and Syst. I, Reg. Papers, vol. 60, no. 11,pp. 2920-2931, Nov. 2013.

[3] A. Agrawal et al., “An 8 x 5 Gb/s Parallel Receiver With Collaborative Timing Recovery,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3120-3130, Nov. 2009.

[4] T. O. Dickson et al., “An 8 x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects,” IEEE J. Solid-State Circuits,

[5] M. Loh and A. Emami-Neyestanak, “A 3 x 9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O,” IEEE J. Solid-State Circuits, vol. 47 ,no. 3, pp. 641-651, Mar. 2012.