使用寬範圍鮑率之頻率偵測器與背景迴路增益控制的時脈資料還原電路

Clock/Data Recovery Circuits Using Wide-range Baud-rate FD and BLGC

姚允升(Yun-Sheng Yao)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2020年)

https://doi.org/10.6342/NTU202000831

摘要

這篇論文的主題主要分為兩個部分，第一部分實現了一個具有寬鎖頻範圍、低功耗與快速鎖定之鮑率數位時脈資料還原電路與1 tap決策迴授等化器。提出無參考時脈之鮑率數位時脈資料還原電路在資料速度16.8Gb/s通過通道之奈奎斯特損耗為10.8dB。提出的頻率偵測器可大幅增加頻率鎖定範圍而不需使用大量比較器。此外將頻率偵測器迴路與相位偵測器迴路分開可降低鎖定時間。 此架構使用台積電40奈米製程，操作在資料速度16.8Gb/s功耗為44mW。
第二部分實現了一個改善雜訊容忍度之數位時脈資料還原電路。提出利用背景校正頻寬的方式改善雜訊容忍度。使用台積電40奈米製程，面積與功耗為0.0324mm2與 12.67mW。在輸入資料速度為1Gb/s與3Gb/s，資料錯誤率<10-12，還原資料方均根抖動量分別為12.3ps與7.74ps。在輸入資料速度為3Gb/s情況下，藉由背景校正頻寬演算法，可使最差的雜訊容忍度提升到0.68UI

關鍵字

鮑率 ； 頻率偵測器 ； 背景迴路增益控制 ； 時脈資料還原電路

並列摘要

This thesis consists of two parts. The first part implements a wide capture range, low power and fast lock baud-rate digital clock and data recovery (CDR) incorporated with one-tap decision feedback equalizer (DFE). A referenceless baud-rate CDR to achieve data rates 16.8Gb/s across a channel with Nyquist loss 10.8dB. Proposed new frequency detector (FD) can enhance capture range without using lots of comparators, achieving wide capture range. In addition, separating the FD loop to control the digital oscillator can reduce the locking time. This baud rate CDR is fabricated in 40-nm CMOS technology operates at 16.8Gb/s data rate with 44mW power consumption.
The second part implements a jitter-tolerance-enhanced digital CDR. To improve the jitter tolerance (JTOL) of a CDR circuit, a background loop gain controller (BLGC) is presented. This CDR circuit is realized in a 40nm CMOS process. Its active area is 0.0324mm2 and the power consumption is 12.67mW from a 1 V supply. For 1-Gb/s and 3-Gb/s PRBS of 215-1 and the bit error rate < 10-12, the measured root-mean-square jitter of the retimed data are 12.3ps and 7.74ps, respectively. By using the proposed BLGC, the minimum high-frequency JTOL at 3-Gb/s is improved to 0.68 UI.

並列關鍵字

baud rate ； FD ； BLGC ； CDR

參考文獻

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