用於百億位元乙太網路(LX4)之多路時脈與資料回復電路

Multi-Channel Clock and Data Recovery Circuit for 10GBASE-LX4 Ethernet

吳則毅(Tse-Yi Wu)

指導教授 ： 曹恆偉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.02518

摘要

隨著網際網路的快速發展與普及，人們對於網路通信頻寬的需求急遽成長，區域網路的頻寬也已在近幾年內跨入百億位元乙太網路的新紀元。在國際電子暨電機工程師協會所制定的百億位元乙太網路規格中，10GBase-LX4 使用低成本的雷射二極體，光二極體及多模或單模光纖作為光通訊的媒介，相信10GBase-LX4 的規格將會在下一代乙太網路中扮演主要角色。
10GBase-LX4　這個規格是一個使用多路接收機（3.125G*4）的應用，這樣的系統不建議使用傳統的鎖相迴路資料回復電路，因為LC壓控振盪器之間會透過基底或是電磁場產生交互影響，所以本論文提出一個讓多路資料回復電路使用同一個振盪器產生之時脈的架構，且能具有低功率及小面積的特性。整個晶片的實現是使用台積電0.18μm 1P6M CMOS 製程，所佔面積為0.8mm * 0.68mm 。在1.8伏特的電壓下總消耗功率為80mW。

關鍵字

時脈資料回復電路 ； 半速率 ； 雙輸入壓控振盪器 ； 多路時脈資料回復電路 ； 百億位元乙太網路(LX4)

並列摘要

With the fast proliferation and development of the Internet, the demand for high-speed communication networks has grown progressively. The bandwidth of local area network (LAN) has also already entered the new era of the 10 Gigabit Ethernet in recent years. By IEEE standard of the 10 Gigabit Ethernet, 10GBase-LX4 specification utilizes low-cost laser diodes, optical diodes, and multi-mode or single-mode fibers. It is believed that 10GBase-LX4 will play an important role in the Ethernet in the near future.
10GBase-LX4 specification is an application of multi-channel receiver (3.125G*4), which is a system not suitable for traditional PLL-based CDR due to the mutual effects of LC-tank VCO caused by the substrate or the electromagnetic field. Therefore, this thesis proposed a architecture for multi-channel CDR to use the clocks generated from the same VCO—a architecture that is not only power-efficient but also space-saving. This 0.8mm x 0.68mm chip is applied to the producing process of TSMC 0.18μm 1P6M CMOS. Its total power consumption is 80mW under the voltage of 1.8 volts.

並列關鍵字

Clock and Data Recovery circuit ； half-rate ； dual-control VCO ； Multi-channel CDR ； 10GBASE_LX4

參考文獻

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