基於奈米級圖樣針對二維自我引導組裝之切斷點重新分佈

Nanoscale Pattern-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly

王占翎(Zhan-Ling Wang)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201702038

摘要

二維自我引導組裝 (two-dimensional directed self-assembly) 是一種次5奈米製程有潛力的候選技術，該技術通過不同的雙重點狀圖樣的組合來確定金屬線的走向。二維自我引導組裝技術中，其運用金屬線末端的切斷點製造出二維圖樣從而獲得想要的線路佈局。同時，為了消除切割光罩之間的距離衝突，它需要重新分佈切斷點的位置。在本篇論文中，我們首次提出方法解決二維自我引導組裝中的切斷點重新分佈的問題。首先，我們將這個問題表述成一個整數線型規劃問題，從而獲得一個最佳解。其次，我們提出一個基於完整模板候選者建立的圖的演算法。邊代表的是模板候選者之間的衝突，這些衝突會在線性時間內被計算。該演算法具有保持最優解的性質，能夠轉化二維自我引導組裝中的切斷點重新分佈問題。它將切斷點重新分佈問題化簡成一個是否選取某個模板候選者的問題，從而被表述成一個二元整數線性規劃問題。這可以被證明是一個很好的方案去更好的處理切斷點重新分佈問題。實驗結果顯示，我們的基於圖的演算法具有高品質與高效率。與基於整數線性規劃的演算法相比，我們基於圖的演算法在切割光罩距離衝突消除和金屬線延長長度最小化兩方面達到最佳解的同時，在速度上平均較快1002倍。

關鍵字

實體設計 ； 製造可行性設計 ； 二維自我引導組裝 ； 切斷點重新分佈

並列摘要

Two-dimensional (2D) directed self-assembly (DSA) is a promising candidate for sub-5nm process technology, which generates routes through various combinations of oriented double posts. In 2D DSA, line-end cuts are employed to fabricate 2D patterns to derive desired layouts, and cut redistribution is applied to eliminate cut spacing violations. In this thesis, we present the first work to handle the 2D DSA cut redistribution problem. We first formulate this problem as an integer linear programming (ILP) problem to obtain an optimal solution. We then propose an optimality-preserving framework, based on a complete template candidate graph, to transform the 2D DSA cut redistribution problem. The spacing violations between template candidates, which are represented as edges, are evaluated in linear time. This framework simplifies the cut redistribution problem to selecting a template candidate or not, which formulates a binary ILP to provide a provably good scheme to better handle cut redistribution problem. Experimental results demonstrate that our graph-based algorithm can effectively and efficiently redistribute cuts with zero spacing violations and minimum wire extensions. Compared with the ILP-based algorithm, our graph-based algorithm can achieve 1002 times faster on average.

並列關鍵字

Physical Design ； Design for Manufacturing ； Two-Dimensional Directed Self-Assembly ； Cut Redistribution

參考文獻

[1] 2015 International technology roadmap for semiconductors, http://www.itrs2.net/itrs-reports.html/.

[2] GUROBI Optimizer, http://www.gurobi.com/.

[3]Y. Badr, A. Torres, and P. Gupta, “Mask assignment and DSA grouping for DSA-MP hybrid lithography for sub-7 nm contact/via holes,” IEEE Transac- tions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 6, pp. 913–926, 2017.

[4]X.-Y. Bao, H. Yi, C. Bencher, L.-W. Chang, H. Dai, Y. Chen, P.-T. J. Chen, and H.-S. P. Wong, “SRAM, NAND, DRAM contact hole patterning using block copolymer directed self-assembly guided by small topographical tem- plates,” in Proceedings of IEEE International Electron Devices Meeting, pp. 7.1.1–7.1.4, Washington, DC, December 2011.

[5]J.-B. Chang, H. K. Choi, A. F. Hannon, A. Alexander-Katz, C. A. Ross, and