超薄氧化層金氧半二極體之電容特徵及記憶體應用

Characterization and Memory Application of Ultrathin Oxide MOS Diodes in the Perspective of Capacitance

黎鎬均(Hao-Jyun Li)

指導教授 ： 胡振國

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201801150

摘要

本論文之研究主要是以電容角度去探討邊緣場效電荷耦合效果，並提出一種雙電容狀態的操作。在此雙電容狀態操作中，吾人可以觀察到記憶體行為。
當鄰近元件之間距足夠小時，各自的電荷會彼此干擾與耦合。因此，一種內側為金氧半電容，外圍是金氧半環狀閘極的元件被設計並實做出來。藉由調變外圍金氧半環狀閘極在不同偏壓(靠近平能帶之反轉區、強反轉區、以及累積區)，造成外圍閘極下電荷載子濃度狀態不同時，量測對應之內側金氧半電容之”電流-電壓”以及”電容-電壓”特性，以討論邊緣場效耦合效果。當外圍閘極處於靠近平能帶之反轉區時，實驗顯示此時電荷載子濃度為耦合效果之主要因子。但當外圍閘極處於強反轉區時，耦合效果不再隨電荷載子濃度上升，因為此時內側電容與外圍閘極間出現可觀的能障，造成耦合效果下降。而當外圍閘極處於累積區時，由於氧化層足夠薄，穿隧注射電流隨著偏壓改變而產生。雖然穿隧注射電流亦有電荷耦合效果，但會受到電容量測時之交流訊號干擾，進而形成大量雜訊。另外，在比較不同頻率下之電容量測結果後，也發現當外圍閘極處於強反轉區時，電容隨著頻率改變而不同；反而當外圍閘極處於靠近平能帶之反轉區電容不隨頻率改變。
除了比較不同偏壓下的電荷耦合效應，也發現浮動閘極與接地閘極對於耦合效應有巨大差異。由於浮動閘極下之電荷較為自由，其電荷耦合效應也較好，可以在內側電容測量得較大的電容值。吾人將浮動閘極下之內側電容較高的電容值視為狀態一，並將接地閘極下之內側電容較低的電容值視為狀態二，在兩狀態間反覆切換並不斷紀錄內側電容之”電容-時間”關係，此種雙狀態電容值操作表現出記憶體特性。當閘極由狀態一改為狀態二時，內側電容值即刻變為低電容值；當閘極由狀態二變回狀態一時，內側低電容值需要相當的反應時間才會變回較高的電容值，這表現出記憶體行為。會影響記憶體行為之反應時間的數種因子也被討論與評估，以供未來設計參考。

關鍵字

金氧半電容元件 ； 記憶體效應 ； 薄氧化層穿隧效應 ； 少數載子耦合

並列摘要

The thesis studies the fringing field carrier coupling effect in the view point of capacitance characteristics. A two capacitance states operation is proposed and demonstrated to have memory behavior.
It is known that the carriers of adjacent devices would interfere and coupling with each other if the distance between them is short. The electrical characteristics of an inner MOS circle with an outer MOS gate ring was measured and studied with three different minority carrier coupling conditions. The I-V and C-V relations was measured with the outer MOS gate ring biased under inversion region (near flat band), strong inversion region, and accumulation region, respectively. When the outer MOS gate ring was under weak inversion region (negative but near flat band bias), the amount of minority carriers was the main factors of minority carrier coupling effects. But when the outer MOS gate ring was under strong inversion region (positive bias), the energy barrier between inner MOS circle and outer MOS gate ring became an important factor since the electron energy level of outer gate decreased. The two factor competes and the energy barrier between inner MOS circle and outer MOS gate ring was the dominant factor when outer gate ring was under strong inversion region. When outer ring was under accumulation region, injection tunneling currents occurred since the oxide was very thin. The injection current sensed by inner MOS circle was strongly disturbed by the AC measurement of capacitance and caused noise in C-V relations. A frequency dispersion behavior was also observed with outer gate ring biased under strong inversion region.
It was observed that floating gate and grounded gate would have quite different impact on carrier coupling effect. The carriers under floating was free to move and respond to AC signals while those under grounded gate was confined by determined electric field and energy level. The high capacitance of inner MOS circle (Cinner) of floating gate can be considered as one state (S1), while the low Cinner of grounded gate can be considered as another state (S2). It was measured that Cinner changed quite fast from S1 to S2, while some transient time was needed for Cinner to change from S2 to S1. This can be seen as memory behavior. Several factors that could affect the transient time were evaluated and explained for future works and designs.

並列關鍵字

MOS capacitor ； memory ； minority carriers coupling ； ultrathin oxide tunneling

參考文獻

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