- 學位論文
適用於不規則低密度奇偶檢查碼之可重配置解碼器晶片之研究
A Reconfigurable Decoder IC for Irregular LDPC Codes
摘要
在論文中，我們提出適用不規則低密度奇偶檢查碼(LDPC)，之可重配置解碼器晶片之硬體架構與實現方式。最常見的LDPC演算法，共有對數域與機率域兩種。而經由系統模擬，我們確定兩種LDPC演算法均可以比迴旋碼中的Viterbi解碼演算法有更佳的效能，而為了降低所需耗費的硬體，我們決定採用對數域演算法，作為硬體實現的目標。為了設計一個可重配置解碼器，有別於一般以繞線為導向的專用解碼器架構，我們採用部分平行化、分散式計算方式，以符合我們的可重配置與一般化的設計目標。此外，為了增加可重配置解碼器的硬體使用效率與吞吐量，我們會先對LDPC中的奇偶檢查矩陣做重排列。若是沒有我們所提出的重排列演算法與執行結果，在現今支援LDPC碼的兩大標準中(IEEE 802.16d與802.11n)，我們的解碼器至少會增加250%以上的硬體消耗，同時吞吐量也會降低一半以上。本晶片的設計流程為半客戶式設計方式：我們使用Verilog XL與HSPICE兩種模擬軟體，分別對數位部分與記憶體部分的電路做模擬驗證。最後我們介紹整個系統的Verilog模擬結果，證實我們的系統的功能是正確無誤的，同時解碼器可以在200MHz時脈速度下，達到30Mbps以上的硬體吞吐量，並且同時支援IEEE 802.16d與802.11n標準中的奇偶檢查矩陣規格。
並列摘要
In this work, we propose an architecture and implementation method of a reconfigurable decoder IC for Irregular LDPC Codes. The two most popular LDPC decoding algorithms are at probability domain and log domain. According to our system simulation, we are convinced that the LDPC code can outperform convolutional codes / Viterbi decoding algorithm. In view of saving hardware cost, we adopt log domain LDPC decoding algorithm as our target of hardware implementation. Due to the realization of a reconfigurable decoder, different from routing-oriented dedicated decoder architecture, we adopt partially parallel and distributed computing hardware to achieve our reconfigurable and generic design concept. On the other hand, in order to increase the hardware efficiency and its throughput, we propose a permutation algorithm applied to parity-check matrix of LDPC code. Without permutation, our generic decoder will need additional 250% hardware cost, and its throughput will decrease by 50% when applied to the two IEEE communication standards, including 802.16d and 802.11n, which both support LDPC codes. The design flow of our chip is semi-custom. That is, we use two different kinds of CAD tools, including Verilog XL and HSPICE, to do simulation / verification on digital and memory circuit respectively. We do complete Verilog system simulation to prove our architecture and circuits are correct and functional-work. In this work, our decoder can achieve 30Mbps date rate operated at clock rate of 200MHz. At the same time, it can support the LDPC parity-check matrix defined in the IEEE 802.16d and 802.11n standards.