在微波多層電路佈局圖中電容與電感的萃取

The extraction of inductors and capacitors from layout of microwave multi-layer circuits

張詠舜(Yung-Shuen Chang)

指導教授 ： 盧信嘉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.02746

摘要

本篇論文可以分為兩大部分。第一部份是有關於元件的萃取，此部份大量應用計算幾何，利用計算幾何並設計演算法來辨識電路元件。電路元件包含電容、電感、分岔與通道。第二部份為電路網路鏈結生成，此部份為設計一演算法，以期能將在多邊形中的電路資訊快速鏈結。可以經由萃取多邊形的點的資訊和邊的關係而生成子網路鏈結，並經由結合全部的子網路鏈結生成全域網路鏈結。此兩部分為佈局對電路圖檢查(Layout vs. schematic check, LVS)之前段作業。

關鍵字

電容 ； 電感 ； 萃取 ； 佈局對電路圖檢查 ； 計算機幾何

並列摘要

There are two parts in this thesis. The first part is about the component extraction, and this part applies a lot of computation geometry algorithms. We use computational geometry to design an algorithm to recognize components. Circuit components extracted include capacitors, inductors, forks and vias. The second part is about netlist generation. In this part, we designed an algorithm to link up all information of polygon effectively. The sub-netlist can be extracted by extracting the point information and the edge relation of polygons, and generate the full netlist. The two parts are the front-end of layout vs. schematic check (LVS).

並列關鍵字

capacitor ； inductor ； extraction ； layout vs. schematic check ； LVS ； computational geometry

參考文獻

[1] Shiu-Ping Chao, Yen-Son Huang, Lap Man Yam, "A Hierarchical Approach for Layout Versus Circuit Consistency Check," Design Automation, 1980. 17th Conference, on 269- 276, 23-25 June 1980.

[3] Tamal Mukherjee, Bikram Baidya, “Extraction and LVS for mixed-domain integrated MEMS layouts,” ICCAD '02, pp. 361-366, 2002.

[8] Lap Kun Yeung and Ke-Li Wu, “A Compact second-order LTCC bandpass filter with two finite transmission zeros,” IEEE Trans. Microwave Theory and Tech., vol. MTT-51 No. 2, pp. 337~341, Feb. 2003.

[12] W. Meier, “Hierarchical layout verification for submicron designs,” Design Automation Conference, 1990.

[2] Todd J. Wagner, “Hierarchical layout verification,” Proceedings of the 21st conference on Design automation, p.484-489, June 25-27, 1984.