SystemC 內容可定址記憶體早期設計驗證的耗電測量工具

A SystemC Content Addressable Memory Power Estimation Tool for Early Design Verification

童顗叡(I-Jui Tung)

指導教授 ： 賴飛羆

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.03163

摘要

因為內容可定址記憶體具有高速搜尋的特性，使得它廣泛地用來實現網路路由器的IP查看表。IPv6中，網路位址增加到128個位元數，因此可以預期內容可定址記憶體的儲存容量將會越來越大。模擬時間是影響上市日期的重要因素。在內容可定址記憶體的早期設計階段使用電晶體層的模擬，例如SPICE，將耗費大量時間並且延遲了產品上市日期。SystemC為系統層級的模擬語言與平台，它提供了較佳的模擬效率以及軟硬體共同設計的能力。然而SystemC並未提供量測耗電量的函式。我們開發早期設計階段SystemC的內容可定址記憶體match-line耗電量測量工具，並建立新的內容可定址記憶體match-line的耗電公式，並模擬了Mibench中十個測量基準，進而將SPICE和SystemC的模擬結果做比較。利用我們的工具，模擬時間平均加快1654倍，而match-line, search-line, storage cell耗電量預估的誤差比平均為14.79%, 11.681%, 3.66%。除此之外我們更提出針對gate-block selection algorithm的低功率改進方案，資料比較次數，錯誤率以及match-line耗電量減少了平均為49%，51%，51%。

關鍵字

內容可定址記憶體 ； 預先計算 ； 低功率 ； SystemC ； SPICE ； 電腦輔助設計工具

並列摘要

Content Addressable memory (CAM) is a storage device which is widely implemented in the IP look-up table of a network router due to its high speed searching performance. In IPv6, the IP address will be 128 bits, as a result, the storage size of CAM will be larger in the future. The simulation time is an important factor affecting time-to-market. Using transistor level simulation such as SPICE in the early design stage of CAM will take huge time and delay time-to-market. SystemC is a system level modelling language and simulation platform, it provides better simulation efficiency and ability of hardware software co-design. However SystemC does not provide the function to estimate power consumption for low power algorithm or structure design. In this thesis, we developed a SystemC CAM power estimation tool (SystemC CAM PET) to estimate match-line power of CAM in the early design stage. We construct a new CAM match-line power model to estimate match-line power consumption. We simulated 10 benchmarks of Mibench and compared our SystemC CAM PET simulation results with SPICE simulation results. The simulation time is shorter in average 1654 and error rate of match-line power, search-line and storage cell estimation is average 14.79%, 11.681%, 3.66%. In addition, our SystemC CAM PET is able to calculate the miss rate, data comparison times, input and search data activity of each benchmark for PB-CAM structure. We also proposed a low power improvement example for PB-CAM structure using Gate-Block selection algorithm and verify it by our SystemC CAM PET. The number of data comparisons, miss rate and match-line power consumption are reduced by 49%, 51%, 51% in average.

並列關鍵字

content addressable memory (CAM) ； SystemC ； pre-computation ； low power ； SPICE ； computer-aided design tool

參考文獻

[1] E. P, et al., "Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines," ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation, 2009.

[4] V. Chaudhary, T. H. Chen, F. Sheerin, and L. T. Clark, "Critical race-free low-power nand match line content addressable memory tagged cache memory," IET Computers & Digital Techniques, vol. 2, no. 1, pp. 40-44, Jan. 2008.

[5] C.-C. Wu, S.-H. Wen, N.-F. Huang, and C.-N. Kao, "A pattern matching coprocessor for deep and large signature set in network security system," in IEEE Global Telecommunications Conference (GLOBECOM), 2005, p. 5.

[6] K. Pagiamtzis and A. Sheikholeslami, "Content-addressable memory (CAM) circuits and architectures: a tutorial and survey," IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 712-727, Mar. 2006.

[7] K. J. Schultz, "Content-addressable memory core cells: a survey," Integration, the VLSI Journal vol. 23, no. 2, pp. 171-188, Nov. 1997.