應用於智慧型標籤基站接收機之低複雜度DQPSK封包接收機設計

Low Complexity DQPSK Packet Receiver Design for Smart Badge Access Point Receiver

黃欐雅(Li-Ya Huang)

指導教授 ： 曹恒偉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201702120

摘要

本論文自訂應用於短距離無線通訊之智慧型標籤(Smart Badge)系統，使用400MHz生醫通訊傳輸頻帶（Industrial Scientific Medical Band, ISM）進行傳輸，傳輸接收的調變方式為差分正交相移鍵控(Differential Quadrature Phase Shift Keying, DQPSK)，因智慧型標籤系統需長時間運作，須具備省電，輕巧的特性，且本系統為多使用者對一基站傳輸系統，各封包會有不同的載波頻率位移及時脈偏移，因此每次接收新的封包需要重新進行同步的估測與補償，且本系統採隨機存取模式通訊協定( random access type)，因此封包到達時間未知，所以我們也設計了封包同步的電路。
本研究設計一具低複雜度、低功耗的小型基站接收機，在AWGN通道且最大載波頻率偏移為400MHz的500ppm，最大時脈偏移為傳送時脈的500ppm的環境下，經過降頻428倍將中頻降至基頻後，先進行封包偵測，再依序進行載波頻率、時脈偏移補償、封包確認及循環冗餘校驗等。定點數演算錯誤率在E_b/N_0等於12dB時達到5×〖10〗^(-5)，和浮點數計算模擬相差0.3dB。硬體實現使用CIC提供的tsmc 90nm CMOS製程，經APR後晶片操作速度為42.8MHz，核心面積為0.48mm^2，面積利用率為75.6%，功耗為14.2mW。

關鍵字

數位訊號處理 ； 封包偵測 ； 低複雜度 ； 架構設計 ； 封包接收機

並列摘要

In this thesis we propose a short-distance wireless communication Smart Badge system, which communicate using the 400MHz ISM bands. Modulation format of the system is DQPSK. Because Smart Badge system should have long standby time, it is designed to save power and have lightweight. And the system is a multiple users system, each packet received at AP may have different Carrier frequency offset and clock offset, so each time we receive a new packet, we need to re-synchronize again. Besides, our system adopts a random access protocol and the its packet arrival time is unknown, so packet synchronization is also necessary.
We design and implement a low complexity, low power Smart Badge base station receiver, which transmitted over AWGN channel, and with a maximum carrier frequency, offset 500 ppm of 400 MHz, and a maximum clock offset is 500 ppm of transmission clock. After down sampled by 428, the IF signal is transmitted to the IF band to baseband, we operate packet detection firstly, and then carrier frequency compensation, clock offset compensation, packet confirmation and cyclic redundancy check. The PER of fixed-point simulation is 5×〖10〗^(-5) at E_b/N_0==12dB, and the difference from floating simulation is 0.3dB. Hardware simulation uses tsmc 90nm CMOS process provided by CIC. The receiver after auto place and routing can operate at 42.8MHz; the core area is 0.48 mm^2 with 68.7% area utilization, and has 11.7mW power consumption.

並列關鍵字

digital signal processing ； packet detection ； low complexity ； architecture design ； burst receiver

參考文獻

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