應用於無線接收機之寬頻低通濾波器與接收信號強度偵測器

自從60-GHz的頻帶開放後，應用在此頻帶的無線通訊系統成為了熱門的研究主題。本論文的重點在於應用於60-GHz接收機的高效能類比基頻電路。在論文中我們提出了5-GHz的信號強度偵測器以及120-MHz的連續時間低頻濾波器。信號強度偵測器一般都是以對數放大器的架構實現，並且得到接受信號強度的近似結果。它包含了一組限制放大器以及一些全波整流器。為了實現寬頻的設計，我們在限制放大器的放大級中採用了主動回授的技巧。此電路採用台積電0.13微米的製程設計，模擬得到的整體增益為41 dB、頻寬為6.8 GHz。此信號強度偵測器的動態範圍大於40 dB，在1.2伏特電源供應下消耗30毫瓦。 120-MHz 的連續時間低頻濾波器採用了主動電阻電容的架構，比起其他種類的濾波器，此架構可以提供較佳的線性度以及動態範圍。為了實現此主動電阻電容濾波器，需要有寬頻的運算放大器。採用的運算放大器採用了前饋式補償技巧，而沒有使用米勒補償電容。對連續時間濾波器來說，元件的變異是非常嚴重的問題，因為濾波器的參數會因此受到影響，例如頻寬、品質因子等等。因此，內建了自動頻率校正電路，以減少元件變異的影響。為了縮短頻率校正的時間，我們採用了連續近似的計數器。此濾波器採用台積電0.18微米的製程製造，可達到120 MHz的頻寬以及21 dBm的IIP3。使用10 MHz的參考頻率量測到的頻率校正時間為，並且在1.8伏特電源供應下消耗43毫瓦。

關鍵字

濾波器；信號強度偵測器；無線接收機

並列摘要

60-GHz wireless communication has been a thriving research topic since 60-GHz unlicensed band is opened. The thesis focuses on the design of high-performance analog baseband circuits for 60-GHz receivers. The presented circuits are a 5-GHz received signal strength indicator (RSSI) and an 120-MHz continuous-time lowpass filter. The RSSI is generally realized in the logarithmic form to approximate the strength of received signals. The structure comprises a limiting amplifier and some full-wave rectifiers. Active-feedback is introduced in the gain cells to achieve wide bandwidth. The circuit is designed in the TSMC 0.13-um CMOS process. The simulated overall gain is 41 dB and the bandwidth is 6.8 GHz. The dynamic range of the RSSI is larger than 40 dB. The total power consumption is 30 mW from a 1.2-V supply. The 120-MHz continuous-time lowpass filter belongs to the active-RC type and provides better linearity and dynamic range than other types. In order to implement the active-RC filter, a wide bandwidth operational amplifier (op amp) is required. Unlike the conventional compensation techniques, the op amp adopts the feedforward compensation technique without using the Miller capacitor. For a continuous-time filter, component variation is a serious problem because the parameters of the filter will be affected, such as bandwidth, quality factor, etc.. Therefore, an on-chip automatic tuning circuit is implemented to alleviate the effect of variations. The SAR scheme is applied in the tuning circuit so as to accomplish short tuning time. This filter is fabricated in the TSMC 0.18-um CMOS process. The filter achieves 120-MHz bandwidth and 21-dBm IIP3. The measured tuning time is about 8 us with a 10-MHz reference clock. The filter consumes 43 mW from a 1.8-V supply.

並列關鍵字

Filter ； RSSI ； Wireless Receiver

參考文獻

[1]R.S. Hughes, Logarithmic Amplification with Application to Radar and EW. Dedham, MA: Artech, 1986.

[2]R. P. Jindal, “Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS,” IEEE J. Solid-State Circuits, vol. 22, no. 4, pp. 512-521, Aug. 1987.

[3]S. Galal and B. Razavi, ”10-Gb/s Limiting amplifier and laser/modulator driver in 0.18-um CMOS Technology,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp.2138-2146, Dec. 2003.

[4]K. Kimura, ”A CMOS Logarithmic IF amplifier with unbalanced source-coupled pairs,” IEEE J. Solid-State Circuits, vol. 28, no.1, pp. 78-83, Jan 1993.

[5]A. B. Williams and F. J. Taylor, Electronic Filter Design Handbook. New York: McGraw-Hill, Inc. 1995.

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應用於無線接收機之寬頻低通濾波器與接收信號強度偵測器

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