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  • 學位論文

高速收發器之抖動注入內建自我測試設計

BIST Design for Jitter Injection of High Speed Transceivers

指導教授 : 黃俊郎

摘要


在現今的高速通訊元件中,抖動已然成為資料可達到傳送品質的重要因素之一,隨著資料傳送頻寬的需求漸增,抖動的規格對高速傳送系統及匯流排來說是相當重要的。一般而言,元件抖動的規格是由自動測試設備(ATE)所測得的,但是資料頻率的提升使的自動測試設備難以趕上期效能的要求。再者,近來大多數研究投注在抖動量測的部分。在本論文中,我們提出了一個內建抖動注入的方法以測試接受器的抖動容忍度,在目標信號頻率1GHz的條件下,這個方法可以注入達240ps 峰對峰值,且高達8 ps解析度的週期性抖動。

並列摘要


For modern high speed communication devices, jitter has been an important factor of the achievable data transmission quality. With the growing demand on data bandwidth, meeting the jitter specification is crucial for high-speed I/O and bus standards. Typically, jitter specifications are tested by external ATE (automatic test equipment), but the elevating data rate makes it difficult, if possible at all, for the ATE to catch up with the performance requirement. Most of the recent works concentrate on jitter measurement methods. In this work, we propose an on-chip jitter injection technique for receiver jitter tolerance testing. With the target clock rate of 1GHz, this technique can inject 240 ps peak-to-peak jitter with 8 ps resolution

參考文獻


[1] Y. Cai, B. Laquai, and K. Luehman, “Jitter Testing for Gigabit Serial Communication Transceivers,” IEEE Design & Test of Computers, vol. 9, no. 1, Jan. 2002, pp. 66-74.
[2] T. Yamaguchi, M. Soma, M. Ishida, H. Musha, L. Malarsie, “A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter,” ITC Proceedings, pp.717-725, 2002
[3] J. Wilstrup, “A Method of Serial Data Jitter Analysis Using One-shot Time Interval Measurement,” ITC Proceedings, pp.819-823, 1998
[4] B. Laquai, Y. Cai, “Testing Gigabit Multilane SerDes Interfaces with Passive Jitter Injection Filters,” ITC Proceedings, pp.297-305, 2001
[6] IEEE Draft P802.3ae, “Supplement to Carrier Sense Multiple Access With Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications,” April 2002.

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