For modern high speed communication devices, jitter has been an important factor of the achievable data transmission quality. With the growing demand on data bandwidth, meeting the jitter specification is crucial for high-speed I/O and bus standards. Typically, jitter specifications are tested by external ATE (automatic test equipment), but the elevating data rate makes it difficult, if possible at all, for the ATE to catch up with the performance requirement. Most of the recent works concentrate on jitter measurement methods. In this work, we propose an on-chip jitter injection technique for receiver jitter tolerance testing. With the target clock rate of 1GHz, this technique can inject 240 ps peak-to-peak jitter with 8 ps resolution