This thesis presents a novel architecture for content-addressable memory with low power feature. This design is based on a proposed voltage compared match line sense amplifier that changes the comparison voltage of CAM word circuit. According to reducing cells on dummy word, we can reach low voltage on each match line and reduces power dissipation of the CAM system. The design was implemented in a 256-word X 144-bit ternary CAM for 1.8V 0.18-um CMOS process. Simulation results show that, for the same search time on TCAM match line, about 30% power reduction can be achieved and for the same current source on TCAM match line, about 25% speed reduction can be achieved.