針對高能量使用效率為目標所進行之數位積體電路設計技巧探究

An Exploration of Power Efficient Digital VLSI Design Techniques

程之奇(Chih-Chi Cheng)

指導教授 ： 陳良基

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2009年)

https://doi.org/10.6342/NTU.2009.02990

摘要

在達到系統規格的情況下降低功率消耗對於目前超大型積體電路(VLSI)設計來說，是一項非常重要的設計方向，也就是以高能量使用效率為目標的設計。我們認為，目前這方面的架構設計可以分為三個大方向：信號處理電路之最佳化、晶片內記憶體之低功率使用以及晶片外記憶體之低功率使用。

本論文探究了高能量使用效率的設計技巧並且提供了五顆晶片之設計與實作作為設計實例。信號處理電路之最佳化已經在文獻中被廣泛地討論，因此在本論文中，將會以晶片內以及晶片外記憶體之低功率使用為主軸。

存取晶片外記憶體所引起的功率消耗通常佔整體系統功率消耗的七成，因此是以高能量使用效率為目標的晶片設計中非常重要的一環。我們在這裡討論三個提升能量使用效率之技巧：嵌入式壓縮、資料重複利用、以及系統晶片整合。我們設計以及實作了三顆晶片以做為晶片外記憶體最佳化的設計的實例：使用於功率感知視訊壓縮系統的嵌入式壓縮/解壓縮晶片可以有效降低視訊壓縮系統中62%的晶片外記憶體存取功率；可調適性視訊壓縮系統中之update stage設計利用晶片內資料之重複利用降低61%的晶片外記憶體存取功率；最後，iVisual整合型智慧視訊感測器系統單晶片利用系統整合完全地消除晶片外記憶體存取的需求。

我們也提出三個技巧以提升對於晶片內記憶體使用之能量使用效率：最小字元長度之分析方法論、晶片內記憶體階層設計、以及降低資料暫存時間。二維多層級的離散小波轉換字元長度分析是我們提出的第一個設計實例，我們提出的分析方法可以在大幅降低分析複雜度的情況下保證避免信號溢位以及達到0.1dB PSNR的分析精確度；我們提出的Multiple-lifting二維離散小波轉換架構利用晶片內記憶體階層可以有效降低78%的晶片內記憶體功率消耗；而最後一個設計實例是使用降低資料暫存時間之JPEG 2000壓縮/解壓縮晶片，記憶體功率消耗有效減少95%。

關鍵字

數位 ； 低功率 ； 積體電路 ； 視覺辨識 ； 影像壓縮 ； 多媒體

並列摘要

Reducing power consumption while meeting the throughput requirement has been important in designing a VLSI for most, if not all, applications. We think most power efficient VLSI design techniques can be classified into the following three categories: power optimization of signal processing circuits, on-chip memory power reduction techniques and off-chip memory power reduction techniques.

In this thesis, those power efficient VLSI design techniques are explored with real design examples. Five chips are implemented and measured to verify the design techniques. The power optimization techniques for signal processing circuits have been thoroughly and systematically discussed in literatures. Therefore, we will lay stress on design techniques for off-chip memory power reduction techniques and on-chip memory power reduction techniques.

Three design techniques about off-chip memory access reduction are discussed. According to the data reported by TOSHIBA, the power consumption of off-chip memory access occupies more than 67\% of the total power consumption in a portable multimedia recording system. We discussed three techniques to reduce off-chip memory access: embedded compression, on-chip data reuse, and SoC integration. Three design examples are provided. A multi-mode embedded compression codec chip reduces 62\% of off-chip memory power in video coding systems; an update-step engine in a scalable video encoder reduces 61\% of off-chip memory power by combining different on-chip data reuse schemes; iVisual intelligent visual sensor SoC eliminates all off-chip pixel data traffic by use of an SoC architecture.

Another three design techniques for on-chip memory power reduction are discussed, and they are on-chip memory bit-width requirement analysis, on-chip memory hierarchy design, and lifetime reduction of intermediate data. There are four design examples shown in this part. A bit-width analysis methodology for multi-level 2-D discrete wavelet transform (DWT) provides a tight upper bound for dynamic range and an accurate round-off error analysis with 0.1dB PSNR prediction error; multiple-lifting 2-D DWT scheme reduces 78\% of SRAM power with an on-chip memory hierarchy scheme; the memory hierarchy design of iVisual also reduces 62\% of total power consumption; a level-switching DWT scheme for JPEG 2000 codec reduces 95\% of SRAM power by reducing the intermediate data lifetime.

In brief, we explore, design, and implement a series of power efficient VLSI design techniques. Hopefully, through the systematic discussion, this thesis can bring some helpful information to designers.

並列關鍵字

VLSI ； SIMD ； Recognition ； Video Coding ； Multimedia

參考文獻

[48] AMBA Specification, http://www.amba.com.

[100] K. K. Parhi and T. Nishitani, “VLSI architectures for discrete wavelet transforms,”

[1] C. Chrysafis and A. Ortega, “Line-based, reduced memory, wavelet image compression,”

[2] International Technology Roadmap for Semiconductors, http://www.itrs.net/.

[3] Sharp Mobile Phone System Solution,