分區關聯度混合式架構應用在預先計算型內容可定址記憶體

Banked-Associative Hybrid Architecture for Precomputation-Based Content-Addressable Memory

林志威(Chi-Wei Lin)

指導教授 ： 賴飛羆

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.03299

摘要

因為內容可定址記憶體廣泛的應用而且可以實做一個查找表功能在一個時脈週期內完成。內容可定址記憶體可以平行比較輸入的搜尋資料和儲存的資料，以提供高速的資料搜尋運作。如果資料搜尋成功代表搜尋的資料和儲存的資料是相符合的，然後內容可定址記憶體會輸出符合資料的位址。在論文中我們提出一個新的架構，應用在預先計算型內容可定址記憶體，其包含了低功率和低消耗的特色。這新的架構結合了關聯度方法和分區方法。結合的結果造成參數記憶體的空間消耗減少，更可以有效的功率節省。經過實驗模擬顯示在功率的消耗上，我們提出的架構相較於ones count預先計算型內容可定址記憶體架構減少47%的功率而在面積的消耗上減少25%，不過有一點延遲產生因為額外的電路設計。

關鍵字

內容可定址記憶體 ； 預先計算 ； 低功率 ； 低成本 ； 分區關聯度方法

並列摘要

Content addressable-memory (CAM) can be used in wide application and implements the lookup- table function within a single clock cycle. CAM compares input searched data with its stored data parallel that provide high-speed data searched operation. If data search is successful, which indicates that a stored data matches the search word, then CAM outputs the address of the matching word. This thesis presents a novel architecture for precomputation-base content addressable memory (PB-CAM) that includes low power, and low cost characters. The new architecture combines the architectural design technique of associative scheme as well as the banked approach. The experimental results showed that the proposed architecture average reduced by 47% power than the ones count PB-CAM architecture and average reduced by 25 % in chip area reduction while a minimal increase of latency that is caused by the additional circuit design.

並列關鍵字

content addressable memory (CAM) ； precomputation ； low power ； low cost ； banked-associative approach

參考文獻

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