手持裝置通訊介面實體層功能性模組驗證環境實作

Verification and Implementation of Bus Functional Model for MIPI M-PHY with UniPro PHY Adapter

張耕力(Keng-Li Chang)

指導教授 ： 郭斯彥

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.10947

摘要

隨著晶片製程微縮到奈米世代，在相同的面積下可以放入更多的電晶體。越來越多的功能被整合進單一晶片中，因此晶片的複雜度也變得越來越高。為了在晶片下線前確認設計的正確性，驗證一直是在晶片設計流程中相當重要的工作，可能佔據其中百分之五十至七十的時間。其中功能性驗證的模擬時間因為晶片複雜度的增加而提高，影大大響晶片設計師的效率。如何快速模擬系統同時達到功能性測試的高涵蓋率因此成為現今晶片設計與驗證工程師需要解決的最重要問題之一。
為了解決上述問題，本論文針對新穎的手持式裝置通訊處理介面實體層(MIPI M-PHY)提出一套匯流排功能性模組(BFM)，實現符合制定規格的行為模型。藉由較高抽象層級的描述模型，可以減少功能模擬所需花費的時間。此外，此功能性模組還具備可參數化的能力以應用在不同的組態環境，以及各種特色功能，例如錯誤注入，使用者可以利用此模組擔任信號的傳送者，送出正常或是違反規格書的信號給待測設計模組，以檢測設計模組的行為與例外處理功能。同時此功能性模組也可以擔任信號的接收者，檢查設計模組是否有違反規格書的行為發生。最後我們提出完整的模擬環境和測試案例供設計工程師使用，使設計者能更有效率的驗證其晶片設計。

關鍵字

MIPI ； 匯流排功能性模組

並列摘要

As integrated circuit manufacturing process migration to nm generation, designer can put much more transistors into the same area. More and more functions are integrated in one SOC, result in the highly increasing complexity of modern chip. To make sure the correctness before IC tape-out, verification is a very important job in IC design flow, and can occupy 50~70% development time. Due to the increasing complexity, functional verification based on simulation also spend too time to fulfill designer’s need efficiently. How to reduce the simulation time and increase functional coverage simultaneously is one of the major issues that design and verification engineer need to solve today.
In this thesis we provide a set of MIPI (Mobile Industry Processor Interface) M-PHY Bus Functional Models (BFM), congruent to MIPI M-PHY specification. These models implemented by higher abstract level description, simulation time can be reduced by testing design-under-verification (DUV) in these models. Besides, these models are configurable and have more features such as “error injection”, we can use these BFM as transmitter to send symbols to DUV to test how DUV will act on exception situation, and also play as a receiver to monitor signals sending from DUV to check if they violate specification’s description. Finally we provide a MIPI M-PHY simulation environment and many test cases to help designers to use these BFM to check their design efficiently.

並列關鍵字

MIPI ； M-PHY ； Bus Functional Model

參考文獻

[1] MIPI Alliance Specification for M-PHY, version 1.00.00, 8 February 2011.

[2] MIPI Alliance Specification for Unified Protocol (UniPro), version 1.40.00, 31 January 2011.

[3] Bishnupriya Bhattacharya, John Decker, Gary Hall, Nick Heaton, Yaron Kashai, Neyaz Khan, Zeev Kirshenbaum, and Efrat Shneydor, “Advanced Verification Topics”, Cadence Design Systems, 2012.

[4] Subramanian Shiva Shankar, and Jayaratnam Siva Shankar, “Synthesizable Verification IP to Stress Test System-On-Chip Emulation and Prototyping Platforms”, in 13th International Symposium on Integrated Circuits (ISIC), Singapore, 2011, pp. 609-612

[5] Sharon Rosenberg, and Kathleen A. Meade, “A Practical Guide to Adopting the Universal Verification Methodology ”, Cadence Design Systems, 2010.