一個具有四倍增益的多輸入環形比較器的高解析度且低功耗之雜訊整形連續漸進式類比至數位轉換器

A 74.6dB SNDR Low-Power Noise-Shaping SAR ADC With a 4x Passive Gain Multiple-Input Ring Comparator

王開(Kai Wang)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201904243

摘要

本論文提出了一個全新的比較器架構，以達到更佳的比較器效率，得以實現一個雜訊整形連續漸進式類比數位轉換器。
一般來說，要實現一個雜訊整形連續漸進式類比數位轉換器，要先做前幾筆殘值資料的取樣，再對取樣後的殘值做積分的動作。而在做殘值資料的取樣時，會因為電荷分享的行為而導致殘值訊號的振幅衰減。同樣的，為了減少功率消耗，本論文使用被動式殘值積分的方法，以省去使用主動積分電路所消耗的功耗，同時也節省電路的複雜度。然而，使用被動式殘值積分的方式同樣會因為電荷分享的行為而導致殘值訊號的振幅衰減。
為了補足損失掉的訊號振幅，通常會利用多輸入差動對的比較器來解決，而這種多輸入差動對的比較器，會因為架構的關係，先天上產生較多的雜訊，對高解析度的類比數位轉換器來說，產生足夠大的影響。同時，比較器中輸入殘值的差動對因為尺寸較大的關係，也會產生更大的返回雜訊，同樣對電路設計造成傷害。
本論文提出的環型比較器，可以解決上述的問題，在不用加大輸入差動對的尺寸的情況下，能彌補電荷分享造成的增益損失，也因為架構的關係，比較器在不引入更多雜訊的同時，功率消耗是跟輸入訊號相關的，使得整體功耗比傳統的比較器還低，以利於高解析、低功耗之類比數位轉換器的設計。
本文所提出的類比數位轉換使用40奈米CMOS製程實現。在0.9V的供電下，所消耗的功耗是14.8微瓦，量測的最高頻寬內的信號與雜訊失真比為75dB，等效為170.3dB的Schreier 效能指標。

關鍵字

雜訊整形 ； 連續漸進式數位至類比轉換器 ； 數位至類比轉換器 ； 環形比較器

並列摘要

This thesis proposes a brand new comparator architecture which improves the ratio between power consumption and input-referred noise, and is combined with a noise-shaping successive-approximation-register analog-to-digital converter (NS-SAR ADC).
To implement a NS-SAR ADC, we need to do the residue sampling first, then the residue voltage will be integrated. Usually, it will generate a gain loss during the passive residue sampling which is done by charge sharing. This gain loss causes the amplitude degeneration of the residue voltage. Besides, in order to reduce power consumption, the passive integration is adopted in this work to avoid the power-hungry active circuit, and reduce the complexity of circuit at the same time. However, the passive integration will also cause degeneration of the residue voltage since the passive integration is also done by charge sharing.
In order to compensate the degeneration of the signal amplitude, multiple-input-pair comparator is often adopted to solve the issue. However, the conventional multiple-input-pair comparator induces more thermal noise than the single-input-pair one does. Thus, the noise shaping SAR faces a tradeoff between noise reduction due to noise shaping and noise increase due to the use of a multiple-input-pair comparator. And the conventional NS-SAR need to consume more power on comparator to reach lower noise level.
This thesis proposes a multiple-input ring comparator with a 4x passive gain to combine with the NS-SAR ADC. It not only has the input-dependent power dissipation, but also gets four times gain amplification of the NS residue voltage to compensate the loss of charge sharing while inducing less thermal noise. It’s useful in the design of low-power, and high-resolution ADC.
Fabricated in 40 nm CMOS technology, the proposed NS-SAR ADC consumes 14.8μW under a 0.9-V supply, and the measured peak SNDR is 75.81-dB. Finally, the Schreier FOM is 170.3-dB for a 42kHz bandwidth at 1MS/s.

並列關鍵字

Noise-shaping ； successive-approximation-register analog-to-digital converter (SAR ADC) ； digital-to-analog converter (DAC) ； Ring comparator

參考文獻

[1] J. A. Fredenburg and M. P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2898-2904, Dec. 2012.

[2] Z. Chen, M. Miyahara and A. Matsuzawa, "A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC," 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, 2015, pp. C64-C65.

[3] W. Guo and N. Sun, "A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator," ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, 2016, pp. 405-408.

[4] H. Tai, Y. Hu, H. Chen and H. Chen, "11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 196-197.

[5] S. Pavan, R. Schreier, and G. C. Temes, Understanding Delta-Sigma Data Converters, 2nd ed. John Wiley & Sons, Hoboken, New Jersey, 2017.