一個四階的連續時間型三角積分類比數位轉換器使用製程電壓溫度不敏感基於反向器的運算轉導放大器與數位噪聲耦合之技巧

A 4th-order Continuous-Time Delta-Sigma Modulator ADC using PVT-insensitive Inverter-based OTA and Digital Noise Couple Technique

龔明緯(Ming-Wei Kung)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202202401

摘要

近期，使用頻率調變連續波雷達來做物件的偵測變得十分熱門，而基頻電路中類比數位轉換器的頻寬跟可以偵測物件的距離是呈正相關的，使用高頻寬的類比數位轉換器可以增加偵測到的距離亦或是減低整體的功耗，因此一個低過取樣率的連續時間三角積分器通常會被用於此應用。
本論文提出兩個一點二五百萬赫頻寬的連續時間型三角積分類比數位轉換器，使用連續離散混和的架構而不是用傳統高階的做法來實現四階的迴路濾波器，兩階使用傳統的迴路，兩階使用數位噪聲耦合之技巧，可以省下兩個運算轉導放大器的功耗；在量化器的選擇上使用了八位元的連續漸進式類比數位轉換器(SAR ADC)，並且重複利用了它的電容陣列來完成噪聲耦合。在傳統迴路上，在第一個作品中，使用了混合米勒與前饋補償的雙級運算放大器 ; 而第二個作品中，則使用了高功耗效率基於反向器的運算轉導放大器(Inverter-based OTA)，並且為了解決在製程與溫度上的變異，提出了一個自動調節電壓的低壓降線性穩壓器，在不同情況下，都可以使此基於反向器的運算轉導放大器有穩定的小訊號表現，並且連續時間三角積分器的解析度都大於70 dB。
此晶片透過台積電TSMC 28 nm CMOS RF High Performance Compact Mobile Computing Plus (HPC+) ELK Cu 1P10M實現，在四十百萬赫茲的取樣頻率下操作，於一點二五百萬赫茲的頻寬下，第一個作品量測到的最大訊號對雜訊與失真比為75 dB，動態範圍為82 dB，整體功耗為0.8 mW，Schreier品質因數為167 dB ; 而第二個作品量測到的最大訊號對雜訊與失真比為69.52 dB，動態範圍為69.2 dB，整體功耗為0.4 mW，Schreier品質因數為164.5 dB

關鍵字

類比數位轉換器 ； 連續時間型三角積分調變器 ； 低功耗 ； 基於反向器的運算轉導放大器 ； 數位噪聲耦合 ； 摺疊電壓隨耦器 ； 低壓降線性穩壓器

並列摘要

Recently, the FMCW radar has been very popular in object detection. The bandwidth of the baseband ADC is related to the object observation range. The ADC with higher bandwidth can either increase the range or reduce the power consumption. Therefore, a low-OSR CTDSM is usually used in this application.
This thesis presents two CTDSM ADCs with a bandwidth of 1.25MHz. Instead of using the traditional high-order loop filter, it uses a CT-DT hybrid architecture to implement a 4th-order loop filter. 2nd-order is implemented in a traditional method, and the other 2nd-order is implemented by the digital noise couple (DNC). It can reduce power consumption by saving two OTAs. The quantizer is chosen to use 8-bit SAR ADC, and its capacitor array is reused for DNC. In the loop filter, the first work uses the two-stage OTA with miller and feedforward compensation, and the second work uses a high power efficiency inverter-based OTA. An LDO that can automatically adjust the supply voltage is proposed to solve the PVT variation. The inverter-based OTA can have stable small-signal performance, and the CTDSM has more than 70 dB over PVT.
Two chips are implemented by TSMC 28 nm CMOS RF High Performance Compact Mobile Computing Plus (HPC+) ELK Cu 1P10M. The prototype modulator is operated at 40MHz. The first work achieves a peak SNDR of 75 dB and 82 dB dynamic range (DR) over 1.25MHz. The overall power consumption is 0.8 mW, and the FoMs is 167 dB. The second work achieves a peak SNDR of 69.52 dB and 69.2 dB DR. The overall power consumption is 0.4 mW, and the FoMs is 164.5 dB.

並列關鍵字

analog-to-digital converter ； continuous-time delta-sigma modulator ； low power ； inverter-based OTA ； digital noise couple ； FVF ； LDO

參考文獻

[ 1 ] A. G. Venon, Y. Dupuis, P. Vasseur and P. Merriaux, "Millimeter Wave FMCW RADARs for perception, recognition and localization in automotive applications: A survey," in IEEE Transactions on Intelligent Vehicles

[ 2 ] R. Ciocoveanu and V. Issakov, "Low-Power 60GHz Receiver with an Integrated Analog Baseband for FMCW Radar Applications in 28nm CMOS Technology," 2021 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2021, pp. 4-6.

[ 3 ] TI AWR1642 Single-Chip 77- and 79-GHz FMCW Radar sensor data sheet

[ 4 ] Shanthi Pavan; Richard Schreier; Gabor C. Temes, "High‐Order Delta‐Sigma Modulators," in Understanding Delta-Sigma Data Converters , IEEE, 2017, pp.83-116.

[ 5 ] B. Wu, S. Zhu, B. Xu, and Y. Chiu, “A 24.7 mW 65 nm CMOS SAR-Assisted CT Delta-Sigma Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR,” IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2893–2905, Dec. 2016.