具有預防性相位鎖定偵測器之可調變頻寬時脈與資料回復電路

An Adaptive Loop Bandwidth Clock and Data Recovery Circuit with Preventinoal Phase Lock Detector

闕禮宏(Li-Hung Chiueh)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.11251

摘要

近年來，由於有線通訊應用與資訊工業的快速成長，高速通訊顯然已成為一個重要的議題。當每秒數十億個位元的訊號藉由銅導線傳遞時，訊號的抖動參數與品質變得更難以估計。其中，接收端內的時脈與資料回復電路(CDR)主要用來重建並還原傳輸端所傳送的資料序列，而頻寬的選擇將直接影響還原訊號的抖動效能。然而，時脈與資料回復電路存在一個取捨問題，介於訊號抖動抑制能力與訊號抖動容忍能力。
在本論文中，一個自適應調整頻寬之資料回復電路被提出來達到還原較佳的訊號品質，其中具有預防性相位鎖定偵測器防止在調整頻寬過程中訊號錯誤率的增加。提出的電路可有效抑制14.14 dB 訊號抖動量在為抖動頻率為8 MHz 的輸入訊號下。自適應調整頻寬電路為全數位合成，整體電路消耗功率為86.4 mW，並操作在6 Gb/s 輸入訊號頻率下，使用的技術為TSMC18 製程。

關鍵字

時脈與資料回復電路 ； 訊號抖動抑制能力 ； 訊號抖動容忍度 ； 自適應頻寬

並列摘要

For the past few years, high-speed data transmission becomes more important in modern communication systems. As the signal bandwidth exceeds gigabit per second for most of copper wire channel, it becomes difficult to estimate the data jitter spectral profile. The clock and data recovery circuit plays an important role in the receivers. The loop bandwidth of CDRs should be chosen carefully to achieve optimal data jitter performance with different jitter spectral profile. However, there is a direct trade-off
between jitter suppression and jitter tolerance for CDRs.
An adaptive circuit is proposed to adjust CDR loop bandwidth based on different jitter spectral profile for better jitter performance. The preventional lock detector (PLD) is employed to achieve better jitter suppression ability without jitter tolerance (JTOL) degradation. The proposed circuit enhances the jitter suppression by 14.14 dB at an 8-MHz sinusoidal jitter source. This adaptive block is fully-digital synthesized and the whole circuit consumes 86.4 mW for a 6-Gb/s input data.

並列關鍵字

Jitter suppression ； jitter tolerance ； adaptive loop bandwidth

參考文獻

[1] B. Razavi, “Design of Analog CMOS Integrated Circuits,” 1st Ed., McGraw-Hill, 2001.

[2] J. Cao et al., “OC-192 Receiver in Standard 0.18-μm CMOS,” in IEEE Intl. Solid-State Circuit Conf. Dig. Tech. Paper, pp. 187-188, Feb. 2002.

[3] B. Razavi, "Design of Integrated Circuits for Optical Communications,” 1st Ed., Mc-Graw Hill, 2003.

[4] J. C. Scheytt, G. Hanke and U. Langmann, “A 0.155, 0.622, and 2.488 Gb/s Automatic Bit Rate Selecting Clock and Data Recovery IC for Bit Rate Transparent SDH Systems,” in IEEE Intl. Solid-State Circuit Conf. Dig. Tech. Paper, pp. 348-349, Feb. 1999.

[5] P. Trischitta and E. Varma, “Jitter in Digital Transmission Systems,” Norwood, MA: Artech House, 1989.