無除頻器之時脈與資料回覆電路及倍頻延遲鎖相迴路

Divider-Less Clock and Data Recovery Circuit and Multiplying Delay-Locked Loop

陳聖宗(Sheng-Tzung Chen)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.10587

摘要

隨著現代科技的發展與進步，可攜帶式裝置在通訊系統上扮演著越來越重要的角色。由於有限的電池容量，低功率消耗成為評斷電路效能的一個重要指標。設計出擁有卓越效能的電路是我們所追求的。
這篇論文主要分為兩個部分，第二章針對倍頻延遲鎖相迴路提出新的架構，利用低頻的參考時脈訊號跟他的輸入緩衝器來產生電路所需的選擇訊號。這個選擇訊號同時還可以提供除頻的功能給倍頻延遲鎖相迴路的回授時脈訊號，除頻後的輸出時脈訊號和參考時脈進行相位的比較。藉由這個方法電路可以關閉除頻器，節省30%的功率消耗。此倍頻延遲鎖相迴路消耗由電源供應器提供的1.0伏特、2.26毫瓦。主動電路面積為0.032平方公厘。
在第三章中，實做一個注入資料鎖定時脈與資料回覆電路，此電路使用功率偵測技術來決定數位控制振盪器的振盪頻率，以產生電路所需的回覆時脈訊號。此功率偵測技術可以取代傳統電路中的參考鎖相迴路或是其他高速邏輯電路，省下大量的功率消耗與電感面積。在輸入為兩百一十億位元每秒之27-1的仿真隨機字串序列下，量測得的位元錯誤率小於10-12。此時脈與資料回覆電路消耗由電源供應器提供的1.1伏特、24.9毫瓦。整體面積為0.23平方公厘。

關鍵字

時脈與資料回覆電路 ； 倍頻延遲鎖相迴路

並列摘要

As the development and advancement of modern technology, portable device plays a more and more important role in the communication system. Due to the finite battery capacity, low power consumption becomes an important target to evaluate the performance of circuits. It is our desire to design the circuits featuring outstanding performances.
This thesis is consisted of two parts. In chapter 2, we propose a multiplying delay-locked loop which uses its low-speed reference clock and input buffers to generate the selection signal. The selection signal even provides the divide function to MDLL feedback clock, and the divided clock output compares the phase error with reference clock. In this method, this MDLL can turn off the divider to save 30% power consumption. Its power consumption is 2.26mW from a 1.0V supply. The active area is 0.032mm2.
In chapter 3, an injection-locked clock and data recovery circuit is presented with power detection technique to calibrate the frequency of digital control oscillator and generate the recovered clock. These power detection circuits take the place of reference PLL or other high-speed circuits in conventional CDR circuits, saving great power and area of inductors. The measured BER (bit error rate) is less than 10-12 for a 25 Gb/s PRBS of 27-1. Its power consumption is 24.9mW from a 1.1V supply. The total area is 0.23mm2.

並列關鍵字

CDR ； MDLL

參考文獻

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