無電感半速率資料與時脈回復電路

An Inductorless Half-Rate Clock and Data Recovery Circuit

王登霖(Tang-Lam Wong)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.03153

摘要

在現代高速通訊中，序列通訊系統的傳輸速度已經達到每秒幾十憶位元．在現在的趨勢下，高速通訊系統的傳輸介質從銅線轉換到光纖．在局域網(LAN)和廣域網路(WAN)資料與時脈回復電路(CDR)的角色．它主要的功能是產生與輸入資料同步的時脈和把輸入資料的抖動量移除．另一方面，現今大部份的高速電路都都是利用互補式金屬氧化物半導體製程(CMOS)是因為它據有低成本，低消耗功率和高度的整合能力．
在設計資料與時脈回復電路時，通常會應用到電感來擴展電路的操作速度．不過，由於電感在晶片中佔據非常大的面積，若要用到電感，晶片的面積勢必大幅度增加．這不利於現在的趨勢, 晶片整合(SOC)．另一方面，資料與時脈回復電路應該可以操作在不同速率增加可應用的範圍．所以在本篇論文提出一個無電感的半速率資料與時脈回復電路．它的操作範圍是6億位元每秒至7.7億位元每秒．電路包括一個能減少回復時脈抖動量和減輕壓控振盪器設計難度的線性半速率相位偵察器，一個俱有兩個獨立調控電壓的壓控振盪器，和一個已經包括頻率鎖定偵測器與不需參考時脈的頻率偵測器．本次晶片是由TSMC 90nm 1P9M CMOS 製程來實現，晶片面積是0.58毫米 x 0.58毫米．輸出時脈的峰對峰值抖動量為78ps，而其均方根值是12.64ps．當輸入資料是6Gb/s 27-1 PRBS時．在操作電壓是1.2伏特下，所消耗的功率為75.2毫瓦．

關鍵字

資料與時脈回復電路 ； 壓控振盪器 ； 線性半速率相位偵察器 ； 頻率鎖定偵測器

並列摘要

In high speed communication, the speed of serial communication has been increased to gigabits per second. The modern trend of high speed communication system converted the transmission medium from copper wire to fibre gradually. In the receiver side of networks, Clock and data recovery circuit (CDR) plays an important role for local area network (LANs) and wide area networks (WANS). The CDR circuit generates a clock that synchronizes with received data and removes the received data jitter. CMOS technologies are often employed in high-speed circuits now because of the low cost, low power dissipation and highly integrated capability.
CDR circuit usually uses inductors to expend the operation rate. However, the chip size must increase seriously because inductors occupy large area in die. It doesn’t benefit the modern trend, system on chip (SOC). On the other hand, the CDR should able to work in different speeds for different specifications. So an inductorless half-rate clock and data recovery circuit (6Gb/s-7.7Gb/s) was proposed. It is composed of a linear half-rate PD which can suppress jitter in retimed data and relax the design difficulty of VCO, a dual tuning VCO which have two independent tuning control voltage in order to reduce the clock jitter, finally, a reference-less FD which includes frequency locked detector that makes the FD is no output after frequency acquisition. The CDR was fabricated in TSMC 90nm 1P9M CMOS technology with an area of 0.58x0.58mm^2. The output clock jitter of this proposed CDR is measured 78ps (peak-to-peak) and 12.64ps (rms) for 6Gb/s 27-1 PRBS. The power dissipation of the core circuit is 75.2mW under 1.2V power supply.

並列關鍵字

Clock and Data Recovery Circuit ； Voltage Control Oscillaotr ； Linear half-rate phase detector ； Frequency locking detector

參考文獻

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