案例研究: RISC-V處理器的測試程式生成應用於軟體自我測試

Case Study: Test Program Generation of RISC-V Processor for Software-Based Self-Test

陳鋐霖(Hung-Lin Chen)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202103446

摘要

近年來，軟體自我測試（Software-Based Self-Test）由於跟生命安全攸關產品和汽車電子產品的高度發展受到更多關注。在本論文中，我們找出更換前一個軟體自我測試方法[1]的待測處理器會發生什麼樣的問題以及解決辦法。從 RISC-V處理器上的實驗結果可以看到，所提出的 SBST方法可以實現 74.36%的轉換延遲錯誤覆蓋率。在這些工作期間，我們發現分支預測會對提出的模板產生了很大影響，因此針對這個問題提出了修改的模板來符合這種技術。而且，在SBST方法中使用到分支有關的操作時，我們提供了更好的定義。此外，為了提高自動化的程度，我們針對當前指令集架構(Instruction Set Architecture, ISA) 配置檔做了修改，並添加了新的配置檔。
通過這個改進的方法，人們可以較少的努力和時間將SBST方法應用在全新的處理器架構上。此外，這個省下來的時間可以針對不同的處理器技術研究對應的新模板。

關鍵字

軟體自我測試 ； RISC-V ； 分支預測 ； 測試樣板 ； 轉態延遲錯誤 ； 超大積體電路測試

並列摘要

Software-based self-test (SBST) has received more attention in recent years due to the high development of life-critical product and automotive electronics. In this thesis, we identify what kind of problems will occur when replacing processor under test (PUT) of previous SBST method [1] and how to fix it. Experimental results on the RISC-V processor show that the proposed SBST method can achieve 74.36% transition delay fault coverage. During these works, we found that branch prediction has a great impact on proposed template, so modified template is proposed to fit this technique. Furthermore, we give a better definition of branch operation when utilizing it in SBST method. Additionally, current ISA configuration file is refined and new configuration file is added to improve the level of automation.
With the improved methodology, people can apply SBST method on brand-new processor architecture with less efforts and time. Further, use the time saved to research new templates for different processor techniques.

並列關鍵字

Software-Based Self-Test ； RISC-V ； Branch Prediction ； Test Template ； Transition Delay Fault ； VLSI Testing

參考文獻

[1] M. Psarakis, D. Gizopoulos, E. Sanchez and M. Sonza Reorda, "Microprocessor Software-Based Self-Testing," in IEEE Design Test of Computers, vol. 27, no. 3, pp. 4-19, May-June 2010.

[2] P. Bernardi et al., "On the in-field functional testing of decode units in pipelined RISC processors," 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, pp. 299-304.

[3] K. Kambe, M. Inoue and H. Fujiwara, "Efficient template generation for instruction-based self-test of processor cores," 13th Asian Test Symposium, 2004, pp. 152-157.

[4] N. Hage, R. Gulve, M. Fujita and V. Singh, "On Testing of Superscalar Processors in Functional Mode for Delay Faults," 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017, pp. 397-402.

[5] P. Bernardi et al., "On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors," 2013 14th International Workshop on Microprocessor Test and Verification, 2013, pp. 52-57.