擁有短重鎖時間鎖頻迴路或頻寬提升技術之次取樣式鎖相迴路

Sub-Sampling PLLs with Short Re-locking-Time FLL or Bandwidth-Enhanced Technique

錢源承(YuanCheng Qian)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2020年)

https://doi.org/10.6342/NTU202004478

摘要

這篇論文的主題主要分為兩個部分，第一部分實現了一個可以忍受電源供應干擾，擁有短的重鎖時間的次取樣式鎖相迴路。使用一個由取樣式相位頻率偵測器，電壓轉電流轉換器，微小死區產生器組成的額外的鎖頻迴路幫助鎖定。在0.18μm CMOS製程下的模擬結果，在除數從45變為44的情況下量測的重鎖時間為0.5μs,在電源供應有很大干擾的情況下模擬的重鎖時間為1.45μs。電路功耗為13.6mW。在鎖相迴路輸出2.2GHz,除數為44的條件下， 模擬的參考突波為-58dB。
第二部分實現了一個擁有一個次取樣式延遲鎖定迴路的次取樣式鎖相迴路,擴充頻寬並得到小的抖動。此外，一個下降緣調整迴路用於使參考時鐘的下降緣與鎖相迴路輸出時鐘的上升緣對齊。此設計的次取樣式鎖相迴路被實現在0.18μm CMOS製程上，總電路的有效面積為0.185mm2。鎖相迴路輸出2.2GHz,除數為44的條件下，模擬的1MHz與4MHz位置的頻帶內相位雜訊分別為-117.4dBc/Hz和121.7dBc/Hz。從100kHz積分到100MHz的均方根時間抖動為441fs,提升91fs。參考突波提升7dB。

關鍵字

鎖相迴路

並列摘要

This thesis consists of two parts. The first part implements a sub-sampling phase-locked loop (SSPLL) to tolerate the supply interference and with a short re-locking time. An auxiliary frequency locked loop (FLL) is realized by using a sampling phase detector, a voltage to current converter and a mini-dead zone creator circuit to help locking. Under 0.18μm CMOS process, the simulated re-locking time is 0.5μs while divider ratio changes from 45 to 44 and is 1.45μs while a large supply interference occurs. The power consumption is 13.6mW. At the output frequency of 2.2 GHz, this SSPLL achieves -58dB reference spur with a division ratio of 44.
The second part implements a sub-sampling phase-locked loop (SSPLL) with a sub-sampling delay-locked loop (SSDLL) to extend the loop bandwidth and achieve the low jitter. A falling-edge tuning loop (FETL) is used to align the falling edge of the reference clock with the rising one of the output clock. The proposed SSPLL is realized in a 0.18μm CMOS process and its active area is 0.185mm2. At the output frequency of 2.2GHz, the proposed SSPLL achieves an in-band phase noise of -117.4dBc/Hz and -121.7dBc/Hz at 1MHz and 4MHz offset frequency respectively with a division ratio of 44 in simulation. Its root-mean-square jitter integrated from 100kHz to 100MHz is 441fs which improves by 91fs. The reference spur is improved by 7dB.

並列關鍵字

PLL

參考文獻

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