以軟硬體共同模擬為基礎的軟硬體協同設計方法 – 使用SystemC以及User Mode Linux

A Co-simulation based Hardware/Software Deign and Verification methodology using User Mode Linux and SystemC

許永泰(Yung-Tai Hsu)

指導教授 ： 王勝德

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2006年)

https://doi.org/10.6342/NTU.2006.03116

摘要

雖然硬體設計技術不斷的快速演進，生產力也隨之水漲船高，但是軟體的生產力卻未能同步的邁進，因此，如何在電子系統的設計初期讓軟體工程師可以及早開始開發，以提升其開發效率的議題日漸重要！因此，基於日漸成熟的Virtual Machine技術(User Mode Linux)以及在System Level Design的未來之星SystemC，我們試圖提出一個的架構來解決這個議題。
在這個架構中，包含了一個以驅動程式為基礎的資料存取方式，使得軟硬體之間的資料傳遞變成可能；中間所需的同步機制則是以GDB以及SystemC內部的signal配合運作完成。
有了這個架構，在設計初期的Co-Simulation將會變成可能；Guest OS所使用的原始碼架構將會盡量維持不變，以提供軟體工程師ㄧ致的開發環境；Guest OS以及SystemC應用程式之間的互動將會盡力將運作時間差的議題做如實的表達，如此一來我們可以有一個新的策略來考慮作業系統的影響，提升設計的正確性！

關鍵字

軟硬體協同設計 ； 軟硬體共同模擬

並列摘要

The paper represents a pure software framework which can be used to assist electrical system level design. The proposed solution basically relies on the interaction between the User Mode Linux virtual machine, which is used to abstract the model of the real programmable device where the embedded software should run, and hardware device simulated by SystemC. In this way, designers will be able to program and validate embedded software as well as the device driver in the early stages of the design flow.
A driver based data access mechanism makes data transmission between simulated hardware and software possible. And the synchronization mechanism is mainly based on GDB and signal in SystemC. The integration of the entire system will be done at run-time.
With this work, there will be a new way to take the impact of operating system into consideration with respect to electrical system design and hopefully it would therefore provide more correctness in design phase

並列關鍵字

Hardware/Software Co-design ； Hardware/Software Co-simulation

參考文獻

[ 2] L. Formaggio, F. Fummi, and G. Pravadelli, “A Timing-Accurate HW/SW Co-simulation of an instruction set simulator with SystemC” In CODES+ISSS`04, September 8-10, 2004

[ 3] L. Benini, D. Bertozzi, D. Bruni, N. Drago, F. Fummi and M. Poncino, “SystemC Cosimulation and estimation of multiprocessor SoC Designs”, In IEEE Computer, Apr. 2003.

[ 4] Z. He, A. Mok, and C. Peng, “Timed RTOS Modeling for Embedded System Design”, In Proceedings of the 11th IEEE Real Time and Embedded Technology and Application (RTAS`05), 2005.

[ 5] A. Gerstlauer, H. Yu, and D. D. Gajski, “RTOS Modeling for System Level Design”, In Proceedings of DATE’03, Germany, pp. 130-135, 2003

[ 7] P. Schaumont, and I. Verbauwhede, “Interactive Cosimulation with Partial Evaluation”, In Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE’04), 2004.