軟硬體共同設計之研究與實作

Design and Implementation of Hardware/Software Codesign for SoC CAD Tool

姜禮安(Li-an Chiang)

指導教授 ： 鄭福炯

大同大學/電機資訊學院/資訊工程學系所/碩士(2004年)

摘要

近來，嵌入式系統的開發人員們正不斷尋找新的工具和技術，以協助滿足在消費性資訊產品與專門工業產品上的爆炸性成長的需求。要及時的躍過嵌入式系統產品的障礙，其中的一項重要關鍵就是結合硬體與軟體系統的設計。除此之外，軟硬體共同設計也是系統單晶片（System-on-a-chip，SoC）設計上的一個關鍵。
進行軟硬體共同設計時，一套容易使用的CAD工具不可或缺。在本篇論文中，我們提出一個新的方法，在FPGA架構上進行軟硬體共同設計；並且發展了一套軟硬體分割工具，整合在我們的SOCAD整合開發工具內。SOCAD包含一個轉換器，能夠將Java程式轉換成基於自時系統技術的VHDL程式碼。
分割演算法使用了省時成本效益（Saving Time Cost Effective）的策略，能夠找出高效益的關鍵函式（method）。分割過程中，FPGA的邏輯元件個數是一項限制條件。分割最後會產生硬體部分的VHDL程式碼與軟體部分的Java程式碼。

關鍵字

分割 ； 軟體數據統計 ； 硬體資訊擷取 ； 軟硬體共同設計

並列摘要

Embedded system designers are constantly looking for new tools and techniques to help satisfy the exploding demand for consumer information appliances and specialized industrial products. One critical barrier to the timely release of embedded system products is integrating the design of the hardware and software systems. In addition to its critical role in the development of embedded systems, co-design is a key design methodology for Systems-on-a-Chip.
CAD tools that can easily help to proceed codesign is necessary. In this paper, we propose a new hardware/software codesign methodology targets reconfigurable architectures (FPGA), and develop a codesign system for our SOCAD tool. The SOCAD contains a translator that can translate Java code into VHDL code based on self-timed cell library.
The partitioning algorithm in the codesign system uses the Saving Time Cost Effective strategy to select the beneficial and critical methods. The number of logic elements to each method is the constraint. There will output VHDL codes for hardware part and Java code for Software part in the end.

並列關鍵字

Hardware Information Extraction ； Hardware/Software Codesign ； Partitioning ； Software Profiling

參考文獻

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