以FPGA實現數位控制之寬輸入電壓範圍單級交錯式升降壓-LLC諧振轉換器

Single-Stage Interleaved Buck-Boost-LLC Resonant Converter for Wide Input Voltage Range Applications with Digital Control using FPGA Implementation

朱勁燁(Jing-Ye Jhu)

指導教授 ： 陳景然

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202102878

摘要

本論文提出了單級交錯式升降壓-LLC諧振轉換器之電路架構，以實現鐵道應用中高達8倍於最小輸入電壓的寬輸入電壓範圍。在本論文中，針對所提出的轉換器進行了分析，包括電路動作原理、增益特性和可實現的輸入電壓範圍，亦計算了組件上的電壓和電流應力，以分析零電壓開關切換 (ZVS) 條件和主要的導通損失。為了開發合適的控制架構，通過將轉換器分成兩級來推導出小信號模型，並利用推導得到的小信號模型，提出了使用脈寬調變控制升降壓級和頻率調變控制 LLC 級的數位控制器架構以及控制器參數設計指南，數位控制器由現場可程式化邏輯閘陣列（FPGA）實現，並由協同模擬的結果驗證了控制器的效果。具有 20-160 V 輸入和 12 V/4 A 輸出之轉換器原型的實驗結果驗證了所提出的直流增益方程式的準確性，並實現了高達最小輸入電壓8倍的輸入電壓範圍，並在工作週期佔空比為0.5時獲得78.2%的最大效率。

關鍵字

交錯升/降壓轉換器 ； LLC諧振轉換器 ； 寬輸入電壓範圍 ； 數位控制 ； 現場可程式邏輯閘陣列(FPAG)

並列摘要

This thesis proposed a single-stage interleaved buck-boost-LLC resonant converter to achieve a wide input voltage range up to 8 times of minimum input voltage for railway applications. In this thesis, analysis of the proposed converter is performed and presented, including operation principles, gain characteristics, and achievable input voltage range. Voltage and current stress on components are also calculated to analyze zero-voltage switching (ZVS) conditions and primary conduction losses. In order to develop an appropriate control architecture, small-signal models of the proposed converter are derived by separating the converter into two stages. With the derived small-signal models, a digital controller architecture using pulse-width modulation to control buck-boost stage and frequency modulation to control LLC stage is presented together with the controller parameters design guidelines. The digital controller is implemented by Field Programmable Gate Array (FPGA), and the co-simulation results verify the effect of the controller. Experimental results of a prototype converter with 20-160 V input and 12 V/4 A output verify the accuracy of the proposed dc gain equation and achieved input voltage range up to 8 times of minimum input voltage. The maximum efficiency of 78.2% is obtained at duty equals 0.5.

並列關鍵字

interleaved-buck-boost converter ； LLC resonant converter ； wide input voltage range ； digital control ； FPGA

參考文獻

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