考慮障礙物及緩衝器之時脈訊號延遲範圍最小化時鐘樹合成

Blockage-Avoiding Buffered Clock-Tree Synthesis with Clock Latency-Range Minimization

鄭仲鈞(Chung-Chun Cheng)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.03393

摘要

在高性能奈米同步數位晶片設計之中，擁有一個能夠高度容忍製程變異的緩衝器時鐘樹是不可或缺的。時脈訊號延遲範圍(clock latency range)，定義為在不同的電壓供給之下的時脈訊號延遲差距，是由2009年的計算機網路綜合國際積體電路實體設計會議時鐘樹競賽(ACM ISPD contest)所提出的時鐘樹合成之主要最佳化目標，它可以用來衡量時鐘樹合成時，製程變異所造成的訊號延遲差距。在此論文中，我們提出了一個流程架構及演算法，可以有效地運用避開障礙物之緩衝器插入技術構建時鐘樹，使其時脈訊號延遲範圍得以最小化。在考慮實際的時鐘樹生成時，我們的策略確保了控制電壓迴轉率(slew rate)和資源的使用符合限制，而這樣的結果乃是經過電路模擬(SPICE simulation)驗證。實驗結果顯示出，比起所有為2009年國際積體電路實體設計會議時鐘競賽的參加隊伍，我們的流程架構以及時鐘樹建構演算法能夠達到最佳的平均時脈訊號延遲範圍值，以及最短的程式運行時間。

關鍵字

時鐘樹 ； 障礙物迴避 ； 控制電壓迴轉率 ； 製程變異容忍 ； 緩衝器插入

並列摘要

In high-performance nanometer synchronous chip design, a buffered clock tree with high tolerance of process variations is essential. The clock latency range (CLR), which is the latency difference under different supply voltages, is defined by the 2009 ACM ISPD Clock Network Synthesis Contest as the ma jor optimization objective to measure the effects of process variation on clock-tree synthesis. In this thesis, we propose a framework which effectively constructs a clock tree by performing blockage-avoiding buffer insertion with CLR minimization. For practical considerations of clock tree synthesis, our strategy ensures that the construction satisfies the slew rate and resource usage constraint which is established by SPICE simulations. Experimental results show that our framework with the clock tree construction algorithm achieves the best average quality for CLR and the least running time, compared to all the participating teams for the 2009 ISPD Clock Network Synthesis Contest.

並列關鍵字

Physical Design ； Clock Tree ； Blockage Avoidance ； Slew Rate ； Variation Tolerance ； Buffer Insertion

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