多重電壓時鐘樹之延遲補償最小化

The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs

鄭曜鐘(Yao-Chung Cheng)

指導教授 ： 黃世旭

中原大學/工學院/電子工程研究所/碩士(2013年)

https://doi.org/10.6840/cycu201300919

摘要

在超大型積體電路設計中，功率消耗(power consumption)的問題變得越來越重要。為了降低功率消耗，多重電壓是常見的技術之一。然而，由於使用多重電壓的方法，在不同的電壓下的路徑延遲(path delay)時間亦不相同，因此會產生時序上差異(clock skew)。在我們的觀察中，以往在多電壓下都是藉由延遲補償的方法來達到時序差異(zero skew)。這種補償方式將造成可觀的面積以及延遲(latency)增加。因此，我們提出了一種線性規劃(linear programming)的方法，利用電路在不同電壓模組的資料路徑中的延遲時間，並以暫存器的到達時間(arrival time)再對時鐘樹做補償，以減少使用不同電壓的區塊之間所補償的延遲元件(delay cell)，並使電路能滿足時序限制(time constraint)。與先前的著作[11]相比，實驗結果表明，我們的方法可以減少約19.08%的補償延遲。

關鍵字

延遲補償 ； 時鐘樹 ； 利用時序差異 ； 多重電壓

並列摘要

In modern VLSI designs, the minimization of power consumption is a very important issue. To minimize power consumption, the use of multiple voltages is a useful approach. However, in a multi-voltage design, the clock skew
control becomes very complicated. Previous works use the delay compensation method to achieve always zero skew among different voltage modes. As a result, a large amount of compensated delay is often required. Based on that observation, in this paper, we try to utilize useful skew among blocks to reduce the amount of compensated delay. We propose a linear programming (LP) approach to formally draw up this problem. Compared with the previous work, experimental results show that our approach can reduce 19.08% compensated delay.

並列關鍵字

multi-voltage ； delay compensation ； clock tree ； useful skew

參考文獻

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[7]K.Y. Lin, H.T. Lin, and T.Y. Ho, “An Efficient Algorithm of Adjustable Delay Buffer Insertion for Clock Skew Minimization in Multiple Dynamic Supply Voltage Designs”, Proc. of IEEE ASP-DAC, pp. 825-830, 2011.

[8]H.M. Chou, H.Yu, and S.C. Chang, “Useful-Skew Clock Optimization for Multi-Power-Mode Designs”, Proc. of IEEE ICCAD, pp. 647-650, 2011.

[9]C.L. Lung, Z.Z. Zeng, et al., “Clock Skew Optimization Considering Complicated Power Modes”, Proc. of IEEE DATE, pp. 1474-1479, 2010.

[17]Usami, K., and Horowitz, M.: “Clustered Voltage Scaling Technique for Low-Power Design”. Proc. Int. Workshop on Low Power Design, pp. 3—8, 1995.