基於FPGA之手寫數字辨識的設計與實現

本論文提出一以FPGA(Field programmable gate arrays)實現類神經網路設計方法，此方法可以在FPGA晶片的有限資源下實現多層類神經網路，最後應用於手寫數字辨識系統中，驗證此系統確實可以加快辨識速度。本論文實現手寫數字辨識神經網路主要分成兩個步驟：(1)將手寫影像與神經元權重輸入的浮點數格式轉化為IEEE754資料格式，讓電路可以進行浮點數的運算，(2)神經元計算會以迭代的方式來設計電路以減少設計資源，並且用Pipeline方式設計電路，以提高類神經網路的計算速度。在實際驗證上，本論文在DE2-70多媒體開發平台上用觸控面板當手寫輸入，透過類神經網路硬體電路做運算。從實驗結果可知所提之類神經網路架構與方法，確實可以提高辨識手寫數字的速度。

關鍵字

現場可程式化邏輯閘陣列；匯流排；嵌入式系統；手寫辨識；類神經網路

並列摘要

This paper proposes a method for implementing neural network-like design using FPGA (Field programmable gate arrays). This method can implement multi-layer neural networks under the limited resources of FPGA chips. Finally applied to handwritten digit recognition system. Verify that this system can indeed speed up identification The realization of handwritten digit recognition neural network in this paper is mainly divided into two steps: (1) Input handwritten images and neuron weights into floating point format and convert to IEEE754 data format, (2) Neuron computing will reduce design resources by iteration, and design in Pipeline method to improve the calculation speed of neural network. In actual verification, this thesis uses the touch panel as a handwriting input on the DE2-70 multimedia development platform to perform operations through neural network hardware circuits. From the experimental results, we can see that the proposed neural network architecture and methods can indeed improve the speed of identifying handwritten digits.

並列關鍵字

Field Programmable Gate Array(FPGA) ； Avalon Bus ； Embedded systems ； Handwritten Recognition ； Artificial Neural Network

參考文獻

[1] L. Boxun, Z. Erjin, H. Bo, D. Jiayi, W. Yu, X. Ningyi, Z. Jiaxing, and Y. Huazhong, ”Large scale recurrent neural network on GPU,“ 2014 International Joint Conference on Neural Networks (IJCNN), pp. 4062-4069, 2014.

Google Scholar

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