使用FPGA實現基於類神經網路之心電圖身份辨識系統

本論文提出使用現場可程式化邏輯閘陣列(FPGA, Field Programmable Gate Array)實現使用心電圖進行身份辨識之系統。心電圖訊號由P、QRS、T波所組成具有因人而異的特徵。此系統以DNN為模型使用心電圖資料訓練，包含一層輸入層一層隱藏層一層輸出層，經軟硬體設計推論運算後與軟體驗算結果可得準確率約為99%，辨識率約為98%。之後將最後輸出層移除後即可得到具有提取心電圖特徵向量之類神經網路，將訓練集以內資料與訓練集外之資料進行特徵向量內積，與訓練集內資料相互特徵向量內積值所設之閥值(Threshold)進行軟體運算比對後可得準確率約為99%。本論文首先將心電圖訊號進行濾波，移除掉原始心電圖訊號中之雜訊，再將連續的心電圖訊號分切成每單位心率之分段資料，以R-peak為心率的中心點，對其取R-peak之前後180個採樣點，將每一個數據進行標準化至1到-1之間。最後將資料進行DNN之全連接層訓練。訓練完成後導出權重與偏置與輸入矩陣之參數以Matlab進行資料轉換為32位元16進制並以Quartus進行硬體結合Nios II軟體協同設計使用100M與50M雙時脈設計運算時間為1.09434ms。

關鍵字

定點數；軟硬體協同設計；辨識身份； DNN ； FPGA ； ECG

並列摘要

FPGA-implemented personal identification with ECG signals based on artificial neural network is presented in this paper. ECG signals have features which are different from one person to another, and its consist of P waves, QRS waves, T waves. This system uses DNN as a model for training with ECG data, including an input layer, a hidden layer and an output layer. Using hardware software co-design could get the accuracy rate which is about 99% and the recognition rate is about 98%.ECG feature vector can be obtained by removing the last output layer ,When I compared the feature vector inner product of the data within the training set divided by the data which is the feature vector inner product of the data outside the training set with the feature vector inner product of the data within the training set divided by the data which is the feature vector inner product of the data within the training set, I can get the recognition rate which is about 99%. At first, the ECG signals are filtered to remove the noise in the original ECG signal, and then the continuous ECG signal is divided into segment data per unit heart rate, and the R-peak is the center point of the heart rate between 180 sample points and 180 sample points, then normalized each data to between 1 and -1. Finally, the data is trained on the fully connected layer of DNN. After the training is completed, the derived weights, biases and input parameters are converted to 32-bit hexadecimal with Matlab, and Quartus is used for hardware and Nios II software co-design. The processing time of the proposed system is 1.09434 ms under dual-clock operation that have clock rate of 50 MHz, and clock rate of 100 MHZ.