低功率高解析三角積分調變器設計：以低速低雜訊與高速多模式應用為例

Design of Low-Power High-Resolution Sigma-Delta Modulators for Low-Speed Low-Noise and High-Speed Multi-Mode Applications

陳信良(Hsin Liang Chen)

指導教授 ： 江正雄

淡江大學/工學院/電機工程學系博士班/博士(2009年)

https://doi.org/10.6846/TKU.2009.00993

摘要

隨著半導體製程技術的演進，電源電壓不斷的降低，信號大小亦隨之降低，唯有降低雜訊與誤差能量，才能在先進製程技術中製作高解析之三角積分調變器，藉由對物理特性上的低頻閃爍雜訊與寬頻熱雜訊的分析、控制與消除，再配合非理想電路的分析與設計始可得到最佳解析度。
本文針對低功率、高解析之三角積分調變器，分別應用於低頻帶與寬頻帶系統做最佳化設計考量與驗證。利用虛擬隨機切流式穩定技術降低閃爍雜訊對低頻帶信號的影響，同時降低調變器的輸出直流偏移電壓，實現一應用於生理信號頻帶之低雜訊調變器。另外，利用雙重取樣技術與多級串接式調變器架構，配合可切換式運算放大器，完成可應用於軟體定義無線電前端接收器之功率最佳化多模式調變器。論文中提出兩種不同應用的三角積分調變器：
其一，應用於生理信號之低雜訊三角積分調變器。使用台灣積體電路公司0.35微米製程，實現在3伏特電源電壓與950微瓦功率消耗之下，可達到92分貝的動態範圍與－135分貝的最低雜訊能量頻譜密度。利用所提出的虛擬隨機切流式穩定技術得到比傳統切流式穩定技術低6分貝的輸出直流偏移電壓，與比相關式雙重取樣技術低1.6分貝之最低雜訊能量頻譜密度。
其二，應用於GSM/WCDMA/WiMAX系統之可切換式雙重取樣多級串接式三角積分調變器。使用台灣積體電路公司0.13微米製程，實現在1.2伏特電源電壓與4.2/11.3/20.2毫瓦功率消耗之下，可達到100/72/75分貝的動態範圍與96/68/71分貝的信號雜訊失真比。利用所提出之可切換式雙重取樣多級串接式調變器架構，實現可多模式切換與功率最佳化之三角積分調變器。

關鍵字

低功率 ； 高解析 ； 三角積分調變器 ； 低雜訊 ； 多模式 ； 雙重取樣 ； 虛擬隨機切流式穩定技術

並列摘要

With the progressing semiconductor process, the signal reduces with the decreasing power supply. Therefore, the only way to implement the high-resolution SDM in the modern process is to reduce the noise power. For reaching the high-resolution, the physical noises of the flicker and thermal ones have to be analyzed, controlled, and cancelled. Meanwhile, to model the circuit nonidealities and noise phenomena into the system design process can optimize the system coefficients for reducing power dissipation.
In this dissertation, low power and high-resolution SDMs are verified with the optimizing system and circuit design for the low and high bandwidth applications. The proposed pseudorandom chopper stabilization technique reduces the flicker noise and the offset voltage for low noise bio-signal SDMs. On the other hand, with switchable operational amplifier, the double-sampled multi-stage noise shaped (MASH) SDM optimizes power dissipation for multi-mode software-defined ratio (SDR) front-end receiver. The proposed SDMs are descript briefly as follows:
The proposed low noise bio-signal SDM is implemented with TSMC 0.35-um process. Using the proposed technique, the modulator achieves 92 dB of dynamic range and −135 dB of noise floor while consuming 950 μW from a 3 V supply. Based on the experimental results, the pseudorandom chopper-stabilization technique has a DC offset voltage that is 6 dB lower than that of the chopper-stabilization technique, and retains a thermal noise floor that is 1.6 dB lower than that of the correlated double sampling technique.
The proposed switchable double-sampled fourth-order MASH SDM is implemented with TSMC 0.13-um process. Using the switchable operational amplifier technique and proposed architecture, the modulator achieves 100/72/75 dB of dynamic range and 96/68/71 dB of signal to noise and distortion ratio while consuming 4.2/11.3/20.2 mW from a 1.2 V supply. Based on the power-optimized strategy from the views of circuit and system, the proposed SDM is a low power multi-mode modulator for the future SDR front-end receiver.

並列關鍵字

Low-Power ； High-Resolution ； Low-Noise ； Multi-Mode ； Sigma-Delta Modulator ； Double-Sampled ； Pseudorandom Chopper-Stabilization ； Software-Defined Radio

參考文獻

[2] T. Christen, T. Burger, and Q. Huang, “A 0.13μm CMOS EDGE/UMTS/WLAN tri-mode ΔΣ ADC with -92dB THD,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2007, pp. 240-242.

[3] K. Vleugels, S. Rabii, and B. A. Wooley, “A 2.5-V sigma-delta modulator for broadband communications applications,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1887-1899, Dec. 2001.

[4] R. Bagheri, A. Mirzaei, M. E. Heidari, S. Chehrazi, M. Lee, M. Mikhemar, W. K. Tang, and A. A. Abidi, “Software-Defined Radio Receiver: Dream to Reality,” IEEE Comm. Magazine, pp. 111-118, Aug. 2006.

[5] A. Baschirotto, F. Campi, R. Castello, G. Cesura, R. Guerrier, L. Lavagno, A. Lodi, P. Malcovati, and M. Toma, “Baseband Analog Front-End and Digital Front-End for Reconfigurable Multi-Standard Terminals,” IEEE Circuits and Systems Magazine, vol. 1, pp. 8-28, 2006.

[7] P. G. Drennan, M. L. Kniffin, and D. R. Locascio, “Implications of Proximity Effects for Analog Design,” IEEE Custom Intergrated Circuits Conference, Sept. 2007, pp. 169-176.