Allegro佈局工具使用與DDRII模擬之特例研究

今日，隨著主流的處理器工作頻率越來越高，因為很多電子產品擁有高速PCB需求特性，印刷電路板空間縮小、印刷電路板零件密度越來越密、轉態速率越來越快、與開發週期越來越短，訊號完整性與電磁相容問題對佈局工作更加嚴峻。因此，設計者應用訊號完整性分析來克服佈局上的問題已成為高速電路板設計流程中重要環節之ㄧ。因此，Cadence的Allegro工具提供完整的印刷電路板設計解決方案，它含蓋了線路圖製作、零件庫管理、印刷電路板設計、訊號完整性分析及電源完整性分析。其設計規範均可透過Constraint Manager平台相互支援直接整合。本研究基於Allegro工具的應用，我們提出一套完整的高速PCB設計流程，供給相關人員使用。設計者可依此將模擬結果與實際印刷電路板做結合，藉此有效提高訊號完整性、減少製作PCB費用、與有效縮短發展週期。最後， DDRⅡ當成設計範例，我們使用Allegro工具產生完整的佈局規則，設計人員可應用這些佈局規則快速完成設計工作。

關鍵字

佈局； IBIS model ；訊號完整度； Constraint Manager

並列摘要

Nowadays, following the working frequency of micro-processor is getting higher; it is more difficulty to conquer the issues of the signal integrity (SI) and electromagnetic compatibility by the layout designers, since electronic products owns the high-speed PCB requirement of the following characteristics, the PCB dimension is narrower, the density of components is denser, the transit state is higher, and the development period is shorter. Therefore, the designers use the SI analysis to conquer the layout issues to become one of the major procedures for the flow of the high-speed PCB design. Therefore, the Allegro tool, which is developed the Cadence design system Inc., has proposed the turn-key solution for the flow of the high-speed PCB design, including the drawing schematic, components management, PCB design, SI analysis, and power integrity analysis. Moreover, the design guide can be created by the Constraint Manager, which is a platform to merge all functions into one. Based on the applications of the Allegro tool, we propose a completed flow for the high-speed PCB design for the designers in this study. They can build the simulation project to compare their simulation results between the PCB layout designs. In such flow, the designers can effectively promote SI, reduce the cost of the implementation PCB, and shorten the development cycle. Finally, DDRⅡ to be as the design example, we employee the Allegro tool to generate the full layout rulers such that the designers can quickly finish their work by these layout rulers.

並列關鍵字

Layout ； IBIS model ； Signal Integrity ； Constraint Manager

參考文獻

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國際替代計量

Allegro佈局工具使用與DDRII模擬之特例研究

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