CMOS脈波寬度控制迴路暨鎖相迴路之分析與設計

Analysis and Design of CMOS PWCL/DLL and PLL

韓松融(Sung-Rung Han)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電機工程學研究所/博士(2004年)

https://doi.org/10.6342/NTU.2004.10216

摘要

當製程技術不斷地提升，電晶體尺寸日益縮小時，各種短通道造成的效應以及電壓、製造和溫度造成的偏移，使得電路設計越來越困難。為了解決這些問題，回授的技術被廣泛地應用在電路設計上。為了能夠鎖定一時脈訊號的相位以及工作週期，鎖相迴路、延遲鎖定迴路、以及脈波寬度控制迴路均被深入的研究。而本論文則主要致力於這三個方面的分析與改善。
在本論文中，分別對脈波寬度控制迴路、脈波寬度控制迴路暨延遲鎖相迴路、以及鎖相迴路進行了深入的探討，而且已在0.35微米的製程中製成晶片。第一個提出來的是一個具有快速鎖定能力的脈波寬度控制迴路以及其電路模型和數學分析。首先，先對傳統的脈波寬度控制迴路作電路分析建立電路模型。接著，根據所建立的電路模型提出新架構並分別推導出傳統架構和新架構的鎖定時間。最後實驗結果確認了我們所作的電路和數學上的分析以及快速鎖定的能力。
第二個提出的是一個新型的單路脈波寬度控制迴路。所設計的新型脈波寬度控制迴路不僅僅能與延遲鎖定迴路一起工作，而且可以減少一個延遲鎖定迴路上的壓控延遲電路，使的此二迴路能有更進一步的整合。藉由所設計的電路，傳統架構上工作週期的精確度必須和對抗製程以及溫度變異的能力來作一取捨的困境可以被消除。控制級的設計上可達到偵測工作週期範圍為100%的能力。除此之外，輸出時脈訊號的工作週期是可預先設定的。
最後，我們將研究重點放在鎖相迴路上。此設計的主要目的有二：自動調整迴路濾波器使其時間常數為一定值以及提供快速鎖定的能力。基於時間常數的固定，可以使得迴路的動態參數(阻尼係數以及自然頻率)可自動追蹤參考時脈訊號的頻率。在快速鎖定的設計上，我們提出了兩個方法。它們可分別減少在鎖定上所花費在頻率的追蹤時間以及相位的追蹤時間。為了比較傳統和新設計的鎖相迴路所需要的鎖定時間，我們提出了一個可以在數學上分析具有cycle-slipping 現象的鎖相迴路的鎖定時間。

關鍵字

鎖相迴路 ； 脈波寬度控制迴路

並列摘要

As the technology continuously scaling down, the short channel effects and the presence of the voltage, process, and temperature variations make the circuit hard to design. For solving these problems, the feedback technique is widely used. To acquire the clock phase and to assure the duty cycle of the clock, it results in the growth of the phase-locked loops (PLLs), delay-locked loops (DLLs), and pulsewidth control loops (PWCLs). This thesis mainly dedicates to the analysis and improvement in these three fields.
In this thesis, a PWCL, a PWCL with DLL, and a PLL were explored and fabricated in the 0.35μm process. First, a fast-locking PWCL with its circuit models and mathematical analysis are proposed. The circuit models of the PWCL are derived first. Based on the circuit models, the lock times corresponded to the conventional and the proposed PWCLs can be calculated. The experimental results verify the analysis and achieve fast-locking capability.
Second, a new single-path PWCL with built-in DLL is presented. This PWCL can cooperate with a DLL and the voltage-controlled delay line (VCDL) in a DLL can be integrated with the buffer line in a PWCL. The trade-off between the duty cycle precision and the robustness against the process and temperature variations can be eliminated. Also, the tuning range of the duty cycle can theoretically be extended to 100% duty cycle. Moreover, the duty cycle of the output clock is presettable.
Finally, the research concentrates on a PLL. The objects of this chapter have two parts: time constant calibration in the loop filter and fast-locking design. Based on the time constant calibration, the loop dynamics, damping factor and natural frequency, can track with the period of the reference clock. In the fast-locking design, two methods are proposed to reduce the lock times in the frequency and phase acquisitions. To compare the lock times spent in the conventional and the proposed PLL mathematically, a method to estimate the lock time in a PLL with the cycle-slipping phenomenon is derived.

並列關鍵字

DLL ； PWCL ； PLL

參考文獻

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