CMOS 寬頻延遲鎖定迴路之設計與應用

Design and Implementation of CMOS Wide-Range Delay-Locked Loop

陳超群(Chao-Chyun Chen)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2008年)

https://doi.org/10.6342/NTU.2008.10705

摘要

隨著金氧半導體製程的日益進步，越來越多的電路被整合在單一的晶片中。而在這些高效能的積體電路中，尤其是微處理器及記憶體系統，時脈產生電路扮演著重要的腳色之一。
在過去，產生時脈信號，減少其延遲時間的方法，是利用相位鎖定迴路來實現。但隨著延遲鎖定迴路的提出，越來越多應用中，已經採用延遲鎖定迴路來取代相位鎖定迴路。原因是相較於相位鎖定迴路，延遲鎖定迴路具有必然穩定及較佳的信號抖動特性。
然而，延遲鎖定迴路存在著鎖定範圍限制的缺點，以致於難以應用在需要寬頻率操作的電子系統中，且難以成為矽智產。尤其是在產生九十度的時脈信號上，輸出信號的精確度則受限於元件本身的匹配程度。為了改善上述的問題，本論文以討論現今技術的限制為出發，並提出改進的方法。
在產生九十度的時脈信號上，論文中提出一個以延遲鎖定迴路為基礎的相位位移電路。所提出的技巧，實現了一個600MHz的相位位移電路，可以產生0o, 90o, 180o 和270o以符合不同應用範圍。
在此論文中，也提出了三種改善傳統延遲鎖定迴路的鎖定範圍限制的方法，使得電路的工作頻率範圍能夠增加。首先是提出改善鎖定範圍的相位偵測器，使得當延遲鎖定迴路輸出信號延遲時間超過鎖定範圍時，能自動校正。我們實現了一個1.5GHz到5GHz的延遲鎖定迴路。其次，我們提出一個壓控三角波延遲線，使得延遲鎖定迴路可於工作頻率下產生0o至360o相位移，因此延遲鎖定迴路的工作頻率範圍得以增加，運用該壓控延遲線的延遲鎖定迴路可工作於50MHz到500MHz。最後，論文中提出一個利用相位偵測輔助電路，來調整壓控延遲線的延遲，來改善鎖定範圍的限制。並且提出一種補償方法，使得電壓源雜訊對控延遲線的影響能夠降低。運用所提出的方法，延遲鎖定迴路的操作電源可由1.4V至0.9V內工作，模擬顯示，當操作電源有10mV的雜訊時，該電路在2GHz的輸出信號抖動為15.9ps。
論文中所提出的四種改進方法，將可使得延遲鎖定迴路在不同應用中提供更佳的可靠度。

關鍵字

延遲鎖定迴路 ； 時脈產生器

並列摘要

With the advance of the CMOS process, more and more circuits are integrated into a single chip. In the high-performance integrated circuits, the clock generator plays one of the important roles, especially in the microprocessor and memory system.
In the past, clock deskew and generation for the quadrature-phase are realized by the phase-locked loops (PLLs). However, with the development of the delay-locked loops (DLLs), it has been widely adopted to replace the PLLs in more and more applications. It is because its unconditional stable and better jitter performance than the PLLs.
However, the DLLs have the finite range problem. It is hard to be applied in the electric system with wide operation frequency range and become a Silicon Intellectual Property (SIP). To generate the quadrature-phase, its accuracy is limited by the matching between components. To eliminate the above problems, this dissertation starts from the discussion of the limitation from previous works and provides the methods to improve its performance.
To have the quadrature-phase clock, a variable phase shift circuit based on DLL is proposed. With this technique, a DLL which generates the phase shift of 0o, 90o, 180o and 270o at 600MHz is presented for different applications.
Three techniques to resolve the range problem of the DLL are also presented. First, a proposed phase detector is described. It corrects the range problem when it occurs and enlarges the operation frequency of the DLL. A DLL based on the proposed technique is designed to operate from 1.5GHz to 5GHz. Second, a voltage-controlled sawtooth delay line is described. With this delay line, a DLL generates phase shift from 0o to 360o from 50MHz to 500MHz is presented. In the end, a window detector is presented to change the initial delay of the VCDL. Therefore, the range problem of the DLL can be avoided. Meanwhile, a compensation technique for reducing the sensitivity for the supply noise on the VCDL is also presented. Utilizing the proposed circuits, the DLL can operate at supply from 1.4V to 0.9V. The simulated peak-to-peak jitter is 15.9ps at 2GHz when supply noise is 10mV.
Four techniques presented in this dissertation make the DLL more reliable for different applications.

並列關鍵字

Delay-Locked Loop ； Clock generator

參考文獻

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