CMOS低壓降線性穩壓器的設計與實作

Design and Implementation of the CMOS Low-Dropout Linear Regulators

呂紹鴻(Sao-Hung Lu)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.00300

摘要

隨著手攜式產品的快速發展，開發低功率消耗的產品以延長電池的壽命已成為現今研究的主題。由於低壓降線性穩壓器具有良好的暫態響應以及低雜訊跟簡單的晶片外部元件等特性，使得其被大量地應用於手攜式產品。然而，傳統低壓降線性穩壓器的穩定度會與其他如暫態響應、最大輸出電流、電流效率、輸出電壓準確度等有所衝突。因此本論文提出幾種不同的方法來改善低壓降線性穩壓器的暫態響應，並且同時維持其穩定度。
一開始我們會介紹低壓降線性穩壓器的一些基本名詞定義跟設計考量。此外，一些規格設計上的衝突也在此介紹，以藉此更清楚地了解設計上的考量。接著我們提出利用單一米勒補償電容的快速回復之低壓降線性穩壓器，以減少一個補償電容以及晶片所占面積。此外，藉由數位控制式動態偏壓電路的使用，當輸出電流由0變到150mA時，對於低寄生電阻和高寄生電阻的輸出電容，此電路皆可快速回復至其穩定值。然而，對於系統單晶片(SoC)的實現上，額外的輸出電容則是一大阻礙。因此，我們提出對任何輸出電容皆可穩定的低壓降線性穩壓器。此外，藉由迴轉率加強電路的使用，在暫態響應上，輸出電壓的下降值可明顯的改善。最後，我們利用頻寬放大的方法，來改善輸出電壓在輸出電流變化上的暫態響應。藉由頻寬放大的方法，所需的米勒補償電容值將可以被大大地減少。此外，經由頻寬放大方法的使用，在暫態響應上，輸出電壓的下降值以及上升值還有穩定時間皆可因而改善。

關鍵字

低壓降線性穩壓器 ； 線性穩壓器 ； 頻率補償

並列摘要

With the larger demand for low-power portable battery-operated electronic devices, there is a growing trend toward lower power consumption to increase the battery life. The low-dropout (LDO) linear regulator is widely used in power management since it has a better load transient response, less output noise and ripples, and few off-chip components. However, there are some tradeoffs among the stability of conventional linear regulators and other performances such as the transient response, maximum load current, current efficiency, and accuracy of the output voltage, etc. Hence, this chapter provides some kinds of different methods to improve the load transient response and maintain the stability simultaneously.
First, we will introduce some terms, definitions, fundamental concepts about the LDO linear regulator. In addition, some considerations and tradeoffs for designing the LDO linear regulator are described to understand the design of the LDO linear regulator more thoroughly. Next, we propose a fast-settling LDO linear regulator with single Miller compensation capacitor. The proposed LDO linear regulator can fast recover to its nominal value for the output capacitors with low and high equivalent series resistance (ESR) by utilizing the digital-controlled dynamic bias circuit as the output load current is switched from 0 to 150mA. However, an additional off-chip output capacitor constraints the application of System-on-Chip (SoC). Therefore, we present a newly designed LDO linear regulator for any output capacitor. The dips of the output voltage can be improved obviously by the use of the slew rate enhancement (SRE) circuit as the output load current is switched from 0 to 150mA. Finally, we use the bandwidth extension skill to improve the output transient response for the output load current variation. By the bandwidth-extension skill, the value of the Miller compensation capacitor is reduced very much. In addition, the dips, peaks and settling time of the output voltage for the load transient response are improved simultaneously by the use of the bandwidth extension skill.

並列關鍵字

LDO linear regulator ； linear regulator ； frequency compensation

參考文獻

[11] Bang S. Lee, “Technical Review of Low Dropout Voltage Regulator Operation and Performance”, Application Reports, Texas Instruments Inc., literature number SLVA072.

[2] K. N. Leung and P. K. T. Mok, “A Capacitor-Free CMOS Low-Dropout Regulator with Damping-Factor-Control Frequency Compensation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, Oct. 2003.

Master thesis, The National Cheng Kung University, 2003

[5] G. A. Rincon-Mora and P. E. Allen, “A low-voltage, low quiescent current, low drop-out regulator,” IEEE Journal of Solid-State Circuits, vol. 33, no. 1, pp. 36-44, Jan. 1998

[7] K. C. Kwok and P. K. T. Mok, “Pole-Zero Tracking Frequency Compensation for Low Dropout Regulator,” IEEE International Symposium on Circuits and Systems, vol. 4, pp.735-738, May 2002