鎖相迴路設計與感測應用

Design of Phase-Locked Loop and Application in Sensor

梁德愷(To-Kay Liang)

指導教授 ： 邱弘緯

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2007年)

摘要

展頻時脈產生器以最不容易受製程變異的電路設計方式，實現展頻技術來解決電磁雜訊的干擾。本論文設計的展頻時脈產生器是以不斷調變可程式化除頻器的除數，使輸出信號的能量平均分散到一定的範圍內，降低各諧波在頻譜上的峰值，由於每一個諧波的峰值都會衰減，因此將可有效降低整個系統所產生的電磁雜訊干擾。本論文所設計的展頻時脈產生器能量衰減量達可11.42dB。
　　頻率合成器在應用在通訊系統時，在系統頻道間距固定的要求下，迫使頻率合成器的頻寬受到限制，為了提升鎖定時間並降低相位雜訊，本論文利用MATLAB設計分數式頻率合成器之模型，結果得到相位雜訊在偏移200KHz時相位雜訊為-100dBc/Hz，雜訊抑制為-60dB/dec。
　　本篇論文為了要改善感測檢測的方便性與實用性，利用QCM 、鎖相迴路、FPGA設計出QCM-Sensor量測系統，以減化傳統複雜的感測步驟和須使用昂貴儀器才能得到感測的結果，並實際量測環境差異和變異量之關係，並探討環境差異對量測精確度所造成的影響。

關鍵字

展頻時脈產生器 ； 分數式頻率合成器 ； 石英晶體微量天平

並列摘要

In order to solve the EMI problem, the spread spectrum clock generator (SSCG) methods reveal the spread spectrum technology, which depends on the circuit design that least process variation. We design the SSCG which is continuously modulated by the divisor of programmable divider, so that spread energy of output signal in specified range and to reduce peak value of every harmonic in spectrum. It is effective to reduce EMI of system because of the peak value of every harmonic would reduce. In this thesis, the SSCG attenuation amount is up to 11.42dB.
　　While applying to the communication system, the fractional-N frequency synthesizer is necessary to simultaneously satisfy the requirement of the channel spacing and loop bandwidth. To improve locking time and reduce phase noise, we used MATLAB to design the model of fractional-N frequency synthesizer. The phase noise at 200KHz is -100dBc/Hz, and noise suppression is -60dB/dec.
　　In order to improve convenience and the accuracy of bio detection, we utilized QCM, PLL and FPGA to design QCM-Sensor Measurement System which decreases complicated steps and doesn’t uses the expensive instrument to get the results of detection against the traditional method. In this thesis, we measure the relationship between the environmental differences and variations, and depict the influence of the accuracy on measurement caused by the environmental differences.

並列關鍵字

SSCG ； Fractional-N Synthesizer ； QCM

參考文獻

[1] D. W. Boerstler, and K. A. Jenkins, “A Phase-Locked Loop Clock Generator for a 1GHz Microprocessor,” Symposium on VLSI Circuits Digest of Technical Paper, pp. 212-213, 1998.

[2] S. O. Jeon, T. S. Cheung, and W. Y. Choi, “Phase/frequency detectors for hight-speed PLL applications,” IEE Electronics Letters 29th, vol. 34, no. 22, pp. 2110-2121, 1998.

[3] S. Haykin, Communication Systems, John Wiley & Sons, Inc., 1994.

[5] B. Razavi, RF Microelectronics, Pretice-Hall, Inc., 1998.

[7] Y. Moon, D. K. Jeong, and G. Kim, “Clock dithering for electromagnetic compliance using spread-spectrum phase modulation,” in IEEE int. Solid-State Circuits Conf. Dig. Tech. Papers, 1999, pp. 186-187.