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  • 學位論文

VDSL接收端晶片設計與實現

Design and Implement of the Receiver Chip for VDSL

指導教授 : 宋國明
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摘要


本研究旨在設計與實現超高速數位用戶迴路(Very High Bit-rate Digital Subscriber Line, VDSL)之接收晶片。近年來,光纖網路的發展相當快速,但還需要一段時間才能全面實行光纖到府(Fiber To The Home,FTTH)服務,因此VDSL傳送與接收器在目前最後一哩中佔了相當重要的角色。 在VDSL接收端部分,主要包含兩大部分,其分別為類比數位轉換器(Analog to Digital Converter, ADC)及可調增益放大器(Variable Gain Amplifier, VGA)。在可調增益放大器部分,由於接收至傳輸線的類比訊號大小變化極大,為符合類比數位轉換器輸入端的輸入位準需求,因此在接收機電路中連接一個可調增益放大器,其動態範圍係以類比數位轉換器的最大輸入位準範圍為限,該電路同時利用共模回授補償以及直流位準消除電路,使得電路輸出更為穩定。在類比數位轉換器部分,使用一個解析度10-bit且100萬取樣率的管線型類比數位轉換器。在前端之取樣保持電路內建比較器與編碼電路實現混合訊號之取樣保持技術,將輸入訊號以類比與數位二種格式儲存,進而降低各階訊號擺幅,放寬了運算放大器對於線性度以及安定時間的要求,並採取運算放大器共享技術,更進一步的達到降低功率消耗與減小晶片面積的目的。

並列摘要


The main theme of this thesis is to design and implementation of the receiver chip of very high bit-rate digital subscriber line (VDSL). Recently, fiber network populated in data communication. However, it need take some time to fully implement the FTTH (fiber to the home, FTTH) service. The development of VDSL transceiver plays an important role in the last mile. This thesis can be divided into two major sections: analog to digital converter (ADC), and variable gain amplifier (VGA). In VGA, becomes that the received analog signal is unknown on the transmission line, a VGA is on demand to modify the amplitude of receivered signal to fit with the input range of ADC. That is, the dynamic range is limited to the maximum input voltage range of ADC. Furthermore, the VGA is more stable not only with a common-mode feedback circuit, but also with a DC offset cancellation circuit to making the circuit to be more stable. In ADC, a pipelined ADC is proposed with a resolution of 10 bits and a the sampling rate of 1 MHz. Moreover, the front-end sample-and-hold circuit is built-in with comparator and decoder to enhance the performance of mixed-mode sample-and-hold technique with reducing the signal swing in a stage. This technique not only relaxes the setting time of operational amplifier, but also mitigate the requirement of linearity. Notify that the power dissipation and chip area are decreased with OPA sharing technique.

並列關鍵字

VDSL VGA Pipelined ADC

參考文獻


[13] 謝晉昇,奈奎斯取樣定理之類比數位轉換器設計,國家晶片系統設計中心,2003。
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[6] Ta, C.M., Chee Hong Yong and Wooi Gan Yeoh, “A 2.7 mW, 0.064 mm2 linear-in-dB VGA with 60 dB tuning range, 100 MHz bandwidth, and two DC offset cancellation loops,” Radio-Frequency Integration Technology, 2005, pp. 74 – 77.
[7] Hui Dong Lee, Kyung Ai Lee and Songcheol Hong, “A Wideband CMOS Variable Gain Amplifier With an Exponential Gain Control,” Transactions on Microwave Theory and Techniques, 2007, pp. 1363 – 1373.

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