高速數位寬頻網路橋接傳送晶片之設計與實現

Design and Implementation of the Transmitter of the High Speed Digital Broadband Network Bridge for Network-on-Chip (NoC)

謝祥圓(Hsiang-Yuan Hsieh)

指導教授 ： 宋國明

國立臺北科技大學/電資學院/電機工程系研究所/博士(2010年)

摘要

本論文旨在設計與實現數位寬頻高速網路橋接傳送晶片。本研究主要是建立乙太網路(Ethernet)與非同步傳輸模(ATM)間之轉換器及橋接器之傳送電路，並搭配時脈管理系統進行資料封包流量的管理，使該轉換器同時享有ATM及Ethernet技術的優點。並將此IC 化成為一種專用晶片(ASIC)，藉此提昇寬頻網際網路的即時切換能力與系統穩定度，同時掌握專用混合訊號晶片的開發與整合技術，有效縮小晶片尺寸，降低生產成本，達到提昇網路產品的技術層次與競爭力的目的。
本論文主要可分為三大電路部份：數位電路、類比電路和混合訊號電路。在數位電路部份，主要是建立開發並整合異位傳輸模(ATM)之轉換器/橋接器上的乙太網路介面及其運作方法，並利用時脈管理系統以先進先出(FIFO)之方式進行資料封包流量的管理，其晶片面積為1.5 × 1.5 mm2，其功率消耗為83.8 mW，傳送資料流通量最高可達173 Mbps。在類比電路部份，我們實現一網路類比前端發射器，該發射機主要包括有:10位元100 MHz之數位類比轉換器及電流模式之全差動線驅動器與低通濾波器三大部份，其晶片面積為1.4 × 1.4 mm2，功率消耗為51.7mW，經由量測後，其輸出電壓可至1.75 Vpp，總諧波失真(THD)為-30.94 dB。最後為混合訊號電路，此為網路傳送電路，包含數位實體層介面、數位類比轉換器、一階低通濾波器以及線驅動器，主要是將網路數位資料透過數位類比轉換器轉成類比訊號，此類比訊號經由低通濾波器過濾不必要的高頻訊號，再輸入至線驅動器，進而將此類比訊號放大並輸出至傳輸線上，以完成發射動作。其晶片面積為2 × 2 mm2，其功率消耗為43.8 mW，傳送資料流通量可達183 Mbps。

關鍵字

數位傳送器 ； 乙太網路 ； 非同步傳輸模 ； 晶片網路

並列摘要

The main theme of this dissertation is to design and implement the network-on-chip (NoC) transmitter for high speed digital broadband network bridge. The main function is to develop a transfer and bridge between Ethernet and asynchronous transfer mode (ATM), and cooperate the management of data packages traffic with clock management system. It makes this bridge take the advantage of ATM and Ethernet technology at the same time. It becomes a kind of an application-specific integrated circuit (ASIC) that can improve the switching of real-time and the system stability in the broadband internet network. It utilizes the mixed-signal design flow that can reduce the chip size, cost, and improve the technological level and competitiveness of networking products.
This thesis can be divided into three major sections: digital circuit, analog circuit, and mixed-signal circuit. In the digital part of this thesis, the main goal is to develop a converter bridge which integrates the interface and operation method of the ATM network and Ethernet. It uses the first-in first-out (FIFO) clock management system to control the traffic of data packages. The chip size is 1.5 × 1.5 mm2 and power consumption is 83.8 mW. The maximum transmission throughput can reach as high as 173 Mbps. Second, we realize a network analog front end transmitter in the analog section. It contains a 10 bits, 100 MHz digital-to-analog (DAC) modulator, a current mode fully differential line driver, and a low-pass filter. The chip area is 1.4 × 1.4 mm2, power consumption is 51.7 mW. After examining via measurement, the output voltage can achieve 1.75 Vpp and total harmonic distortion (THD) is -30.94 dB. The last section is a mixed-signal circuit for a network transmission circuit. It includes a digital physical layer interface, a DAC modulator, single order low-pass filter, and a line driver. The main function is to transmit the network data to the transmission line. It transforms the network digital data into analog signal with a DAC modulator. After filtering the unnecessary high-frequency signal, low-pass filter imports this signal to line driver. The line driver will amplify and export this signal to the transmission line in order to finish the transmission procedure. The chip size is 2 × 2 mm2, power consumption is 43.8 mW, and the maximum transmission throughput can reach as high as 183 Mbps.

並列關鍵字

Digital Transmitter ； Ethernet ； Asynchronous Transfer Mode (ATM) ； Network-on-Chip (NoC).

參考文獻

[3] S. E. MINZER, “Broadband ISDN and asynchronous transfer mode (ATM),” IEEE Communication Magazine, vol. 27, no. 9, pp. 17-24, 57, Sep. 1989.

[4] A. Sheibanyrad and A. Greiner, “Two efficient synchronous ⇔ asynchronous converters well-suited for network on chip in GALS architectures,” Integration, the VLSI Journal, vol. 41, pp. 17-26, 2008.

[5] I. M. Panades, A. Greiner and A. Sheibanyrad, “A low cost network-on-chip with guaranteed service well suited to the GALS approach,” International Conference on Nano-Networks and Workshops, Sept. 2006, pp. 1–5.

[7] F. Calvo, P. Plaza and P. Mateos, “ICM2 IC: A new ATM switching element for 2.48 Gb/s communications,” in Proc. of the EDAC, European Design and Test Conference, 28 Feb.-3 Mar. 1994, pp. 65 – 69.

[8] T. Kessler and W. Henkel, “Simulation of ADSL over ISDN on german subscriber lines,” IEEE Communications Letters, vol. 1, no. 5, pp. 124 – 126, Sept. 1997.