摘要
本論文旨在製作一適用於VDSL網路系統，且操作頻率為200 MHz之CMOS數位發射機，主要包含有12位元200MHz之數位類比轉換器及電流模式全差動線驅動器兩個部份，並採用TSMC 0.18 μm 1P6M CMOS製程技術來實現。 為了達到高速操作頻率的需求，故採用電流切換式之數位類比轉換器架構。本論文使用區段式數位類比轉換器來實現，以3位元二進制碼加上9位元溫度計碼，合成12位元數位類比轉換器。再利用緩衝器的概念，於電流源的輸出端加上一緩衝器，及配合門閂電路將各區段波形匹配，以降低突波現象。此外，為了將數位電路之佈局面積與複雜度做最佳化之設計考量，本論文將9位元之溫度計碼拆為3位元加6位元的溫度計碼解碼架構，以減少數位解碼電路的面積。在佈局方面，為了減少消除梯度效應及線性誤差，使用電流源陣列。最後實現輸出最大電流、INL及DNL分別為4095 μA，0.32及0.39 之12位元數位類比轉換器。 就線驅動器而言，為了產生較高的功率效益(Power Efficiency)，分別利用兩條不同的電壓源路徑，以避免電壓源路徑疊加，藉以實現低電壓的電路設計，以及採用合成(Synthesis)的方式，此合成電路能產生輸出阻抗匹配電阻，藉以降低電路的功率消耗、提升功率效益。此外，本論文進而利用濾波電容及對大寄生電容端點提供前饋的充放電路徑以及線驅動器後級加上電流回授補償電路，以抑制諧波失真問題，並提高線性度。本線驅動器在1.8 V的供應電壓下，能驅動100 Ω輸出端負載，產生100 MHz與2 VPP的電壓訊號振幅。
並列摘要
This thesis describes the chip implementation of a 200 MHz CMOS digital transmitter based on VDSL system specification. which is composed of a 12-bit, 200 MHz digital to analog converter, and a fully differential current-mode line driver. The digital transmitter had been fabricated with the TSMC 0.18 μm 1P6M CMOS technology. For high-speed application, the digital to analog converter adopts the switch-current mode architecture. This is a 12-bit digital-to-analog converter (DAC) is implemented with M-bit segmented, which is implemented with 3-bit binary and 9-bit unary. Buffers are used to isolate the output of digital circuit and to reduce the glitch of current. Furthermore, in case of achieving small layout area, reducing the complexity of digital circuit, 9-bit unary is composed with the 3-bit and 6-bit thermometer-encoding architecture. In order to mitigate the process variation and linear error, current source array (CSA) is applied. The simulation of 12-bit DAC shows that the max current is 4095 μA, the integral nonlinearity (INL) and the differential nonlinearity (DNL) are 0.32 LSB and 0.39 LSB respectively. In order to have high power efficiency, in line driver the utilization of impedance synthesis is to eliminate the matching resistor which works with extra power consumption. Furthermore, the capacitive feed-forward path is introduced used to reduce the crossover distortion; and that the current-feedback circuit is added to increase linearity. According to the simulation result the output voltage of the proposed line driver is 2 VPP at differential load of 100 Ω, the power supply of 1.8 V and the operating frequency of 100 MHz.