本論文主要是利用硬體描述語言,來撰寫即時影像自動亮度控制的硬體架構,並以現場可程式邏輯閘陣列,實現及驗證其功能;其設計原理係採用計算影像的亮度值(Intensity),計算每一張畫面的平均亮度,於計算得到整張畫面的影像平均亮度後,可判斷影像的亮度是否合宜,再經由自動亮度調整機制,將下一張畫面影像調整至適當之亮度值,使得視覺上更為舒適。 在這個架構中,連續影像畫面由CMOS 影像感測器獲取,每一張畫面的圖像格式為彩色貝爾格式圖像,經此格式圖像轉換為RGB 三原色,同時再將RGB 三原色的數值轉換成亮度值,轉換方式非使用RGB 轉YCbCr的公式計算,這是由於轉換YCbCr需要之浮點運算與乘法運算,對現場可程式邏輯閘陣列(FPGA)的架構而言,必需有相當多的邏輯資源。因此,本論採用位移計算的方法計算像素亮度,並以靜態影像平均亮度計算方法為基礎加以修正改進,進而能夠於即時動態影像中調整其畫面亮度。 最後實驗結果顯示,當影像亮度偏低時,能夠透過自動亮度功能將影像調整至適當亮度;反之,當影像亮度偏高時,亦能夠將畫面調整至適當亮度,以證明本論文提供的方法,是能夠改善畫面亮度品質。
In this thesis, the verilog HDL is used to develop a hardware architecture of real-time image automatic brightness control. It is implemented and verified with FPGA technology. Firstly, an averaged intensity per frame is calculated with its intensity of every pixel in a frame. Secondary, the calculated averaged intensity is used to evaluat the brightness of the frame. If the brightness of this frame is not suitable, it is necessary to adjust the intensity value of next frame to have a proper intensity. The destination is to make the image more clear and comfortable. In the proposed architecture, the image date is captured from CMOS image sensor, and that the data format of a frame is the Bayer color pattern which is need to be converted into the format of RGB data, the RGB data can be used to calculate average intensity per frame. In this study, the YCbCr formula is gave up for the complex calculation of floating point and multiplication with FPGA technology. That is it needs more fabric logic resource to complete those two operations of floating point and multiplication. A rapid shift method is adopted to calculate the brightness of a static image. The fast calculation makes it true to adjust the brightness of image not only real-time but also automatically. According to the experiment result, a low intensity real-time image can be adjusted to a suitable intensity using the automatic brightness control. On the other hand a high intensity of the image can also be adjusted to a suitable one by the same function. The goal of this thesis is to provide an integrated FPGA with real-time image algorithm to improve the quality of a real-time image.