馬達閉迴路控制系統之混波晶片設計

Mixed-mode chip design for the closed-loop control of motor system

黃書緯(Shu-Wei Huang)

指導教授 ： 蔡孟伸 ； 宋國明

國立臺北科技大學/機電學院/自動化科技研究所/碩士(2005年)

https://doi.org/10.6841/NTUT.2005.00072

摘要

本論文主要是以Cell-based製作流程，並使用台積電0.35微米2P4M（TSMC .35 m 2P4M）的製程技術來研發馬達閉迴路控制系統之混波晶片。所設定的規格為直流偏壓電源3.3V、功率消耗20.51mw、工作最高頻率為100MHz。並且在國家晶片中心前瞻性晶片D35-94B(F)完成下線。
整體架構大致可分為數位和類比電路二大部份，數位部份可分為：空間向量脈波寬度調變器、簡易中央電腦處理器、比例積分控制器、降頻濾波器。空間向量脈波寬度調變器架構包括了：輸入訊號、計算級電路、脈波寬度調變信號產生器、保護時間產生器。最後輸出級產生控制訊號來驅動後級變頻器，而後級變頻器驅使馬達轉動。簡易中央電腦處理器為整個數位部份的核心，可將馬達動作命令寫入暫存器當中，再透過空間向量脈波寬度調變控制器來控制馬達。比例積分控制器專門針對馬達速度迴授控制所設計的。降頻濾波器將類比電路的三角積分調變器輸出的調變碼轉為二進制碼。類比部份為：取樣保持電路、電流比較器、數位類比轉換器。構成了一個完整的三角積分調變器。
數位部份以非常高速積體電路的硬體描述語言(VHDL)來編寫系統架構，類比電路以Hspice模擬軟體來驗證其功能正確與否。本研究已將整體IC製作流程完成，並且驗証最後的Post-layout Simulation的輸出波形都是正確無誤的，表示數位電路和類比電路均可正確動作。

關鍵字

空間向量脈波寬度調變 ； 硬體描述語言 ； 以標準單元為主(Cell-based) ； 三角積分調變器 ； 取樣保持電路 ； 電流比較器 ； 數位類比轉換器

並列摘要

The main research of the thesis is based on Cell-based digital IC design flow, and is designed to use the TSMC 0.35 m 2P4M cell library to develop the closed-loop control of motor system. The regulated specifications are DC 3.3 volts, power consumption 20.51mW, and system max frequency 100MHz. Also, it is manufactured at D35-94B (F) of the CIC’s advance chip.
The whole structure is divided into a digit and an analog circuit .The digital part contains space vector pulse width modulation, simple center computer processor, proportional-integral controller and descend frequency decimator. Space vector pulse width modulation includes input circuit, calculate circuit, pulse width modulation signal generator and dead time generator. Output stage generates the control signal to drive the inverter, and the inverter makes the motor rotate. Simple center computer processor is the core of the digital part; the movements of the motor can be written into the register, and then simple center computer processor can control motor through the space vector pulse width modulation. Proportional-integral controller was designed for the closed-loop of the motor specially. Descend frequency decimator can change the modulation code into binary code. Analog part includes sample and hold circuit, current comparator and digital analog convert. They form a complete Delta-Sigma Modulator.
The system is constructed by VHDL (Very High Speed Integrated Circuit Hardware Description Language) in the digit part. By Hspice simulation, the analog circuit implementation is finished. The thesis has already made the motor control IC design flow successfully, and has verified Post-layout Simulation is correct, indicating that the digital circuit and the analog circuit are both correct.

並列關鍵字

space vector pulse width modulation ； HDL ； Cell-based ； delta-sigma modulator ； sample and hold circuit ； current comparator ； digital analog converter

參考文獻

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