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  • 學位論文

低抖動鎖相迴路之設計

Design of Low Jitter Phase-Locked Loop

指導教授 : 黃育賢 陳建中

摘要


由於鎖相迴路中使用的每一個元件均會貢獻雜訊而影響其抖動量。另外在晶片系統中,供應電源與基板也會注入雜訊至鎖相迴路,其惡化抖動量(jitter)甚鉅。因此本論提出改善方式進而降低抖動量,包括在電荷充放電路(Charge pump)中增設自我調整機制以消除輸出電流之不對稱,此舉亦可加大電壓控制震盪器(Voltage-controlled oscillator)的控制電壓範圍。理論上三階迴路濾波器(Loop filter)要比二階抗雜訊能力來的好,不過也因其迴路頻寬較小而致使系統鎖定時間的延長。同時本電路提出一切換機制並適當地切換此兩種形式迴路濾波器以獲取彼此的優點;為因應其切換機制必須把整個迴路濾波器整合至單一晶片上,故晶片面積的節省以及雜訊之隔離皆是電路設計上的課題;在此以電容放大電路避免消耗過多晶片面積。額外加入的低壓降線性穩壓器(Low dropout voltage regulator)則是有效阻絕雜訊回灌並提供一穩定的電壓予迴路濾波器。在整個系統中占重要地位的電壓控制震盪器是一極敏感元件,我們利用粗調與細調的機制供給電流予延遲單元,其可調整壓控震盪器之增益以降低外界雜訊干擾。

並列摘要


Each device has been employed in PLL would contribute the unavoidable noise to degrade the jitter performance. In addition, the power/ground and substrate noise injected to PLL which integrated in a chip also aggravates jitter heavily. This thesis proposed some improvements for the essential issue of low jitter. We consequently improve the circuit architecture of each device and described it as following. One of that is to add self-adjusted mechanism into a charge pump to eliminate whose output current mismatch; furthermore, the mechanism is capable to extend the control voltage range of Voltage-controlled oscillator (VCO). On the other hand, because of the third-order loop filter with smaller bandwidth, it performs better noise suppression ability than the second-order loop filter does; nonetheless, the third-order presents longer acquisition time. In order to obtain the advantages of both two types of loop filters, a proposed switching mechanism has been utilized to select them appropriately. To accommodate the switching mechanism, we design the loop filter for monolithic integration; as a result, both saving silicon area and isolating noise are main concerns while designing it. By using capacitor multiplier to avoid large amount silicon occupation and utilizing an additive low dropout voltage regulator (LDO), the noise injection can be isolated and a stable supply voltage is also provided for the loop filter. The VCO plays an important role in the whole system whereas it is an extremely sensitive device. Therefore, coarse and fine tuning mechanisms are employed in current-starved elements for delay cells that can lead to the VCO gain (KVCO) tunable and then mitigate the disturbance of external noise.

並列關鍵字

PLL Jitter Charge pump VCO Loop filter LDO

參考文獻


[2] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.
[3] C. W. Lai, “Design of low-jitter adaptive bandwidth PLL based on self-biased techniques,” Master thesis, NCU, Department of Electrical Engineering, June 2005.
[4] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 331-343, March 1996.
[5] P. Larsson, “High-speed architecture for a programmable frequency divider and a dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol. 31, no. 5, pp.744-748, May 1996.
[6] H. H. Chang and J. C. Wu, “A 723-MHz 17.2-mW CMOS programmable counter,” IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1572-1575, Oct. 1998.

被引用紀錄


顏士博(2009)。以相位/頻率偵測器自動調整之電流模式主動濾波器設計與實現〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-1808200917112300
陳俊宇(2010)。利用延遲鎖定迴路技術之自動調整切換式電容濾波器設計〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-1308201021240500

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