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  • 學位論文

具彈性架構的高速硬體倒傳遞類神經網路設計

Design of High Speed Hardware Back Propagation Neural Network with Flexible Structure

指導教授 : 蔡孟伸
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摘要


類神經網路最主要的特性就是高度平行運算架構,而每一層的節點間相互連結,形成了一個能夠處理複雜工作的網路。由於在軟體上計算類神經網路相當耗時,本論文設計了一套根據倒傳遞網路運算模式而建構出來的硬體運算架構,採用了多重性運算單元陣列方式及單指令多匯流排架構,並利用管線設計方式提高速度。本文目的在於開發高速彈性設計類神經網路硬體,且具有回想及線上學習功能,改善了以往類神經網路環狀硬體架構。分段計算為本文主要提出的重點,利用分段計算可使控制器以固定運算單元陣列下,去計算合成出龐大的網路,此後神經元的數目便可以動態改變。以Nios II當作下達指令、網路架構參數的微處理器,而其系統時脈採用100Mhz,利用控制器分配權重設計及控制流程,使其不需要重新規劃及設計整個系統。由於是在硬體上完成開發,因此在移植性方面及運算速度上都比軟體上開發來的便利及快速,適用於低階嵌入式系統內。最後,透過應用在雜訊過濾、曲線擬合、分類以及即時多工系統上,驗證本論文所提的架構之執行效率可以達到高速運算的需求。

並列摘要


The main characteristic of Artificial Neural Network(ANN) is its highly parallel arithmetic structure. Neurons are inter-connected among each layer to form a very complex structure which can be used to solve complex non-linear problems. Most of researchers implemented ANN in software in the past due to its flexibility. However, the software-based ANN suffers from the performance problem. This thesis tried to implement the ANN in hardware to alleviate the drawbacks of software-based ANN. Multiple process elements (PEs) array and SIMD (Single Instruction Multiple Data) structure is used in this thesis to implement an ANN. The developed ANN has both recall and on-line learning capability. Piece-wise calculation is also proposed in this thesis. By using piece-wise calculation, a larger ANN structure can be formed by a limited number of PEs. Since the number of neurons in the ANN can be dynamically changed during the calculation of ANN, the proposed ANN structure can be easily applied to different application, especially in the low-end embedded systems. Finally, three test cases, e.g., noise filtering, curve fitting and classification, were used to evaluate the performance and validate the results. The results show that the proposed ANN structure is able to complete the calculation within few microseconds during recall stage.

參考文獻


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被引用紀錄


葉彥智(2010)。具彈性架構的高速硬體倒傳遞及回饋型類神經網路設計〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://doi.org/10.6841/NTUT.2010.00465
傅耀賢(2009)。高效率倒傳遞類神經網路的平行學習架構設計〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-2107200920534500
詹雅宇(2011)。具自由回饋節點的高速硬體倒傳遞及回饋型類神經網路設計〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-1808201112271000

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