以FPGA開發手部動作辨識系統 之類神經網路晶片

Develop an Artificial Neural Network Chip Using FPGA for Hand Motion Identification System

吳靜宜(Ching-Yi Wu)

指導教授 ： 徐良育

中原大學/工學院/醫學工程研究所/碩士(2004年)

https://doi.org/10.6840/cycu200400644

摘要

摘要
本研究之長程目標為利用表面肌電訊號(SEMG)之特徵值發展出一套可辨識手部動作之系統，並選擇倒傳遞類神經網路演算做為手部動作辨識之核心。本研究之先期研究已完成七通道主動電極SEMG擷取系統，當取得SEMG並計算其特徵值後，即可提供網路輸入之用。由於目標之系統必須為可攜式，利用數位訊號處理晶片(DSP)以軟體實現複雜之類神經網路運算將佔據太多DSP的資源，也無法達到即時(real time)之快速要求。設計特殊晶片雖能加速運算，減少軟體的複雜度，但是所需的發展時間較長。另一方面，場效式可程式閘陣列(FPGA)在硬體實現中提供一個過渡且易於除錯的方案，因此本研究採用FPGA硬體實現的方式，實現一具有學習功能之類神經網路晶片，利用主從式架構以減少DSP的運算負擔。
本研究先以Matlab軟體模擬類神經網路之運算，以驗證演算流程之正確性，降低日後晶片設計除錯之難度，待軟體測試無誤後，再邁入硬體開發與測試流程。軟體測試利用Matlab toolbox內建之類神經網路與Matlab類神經程式對照，用以驗證演算流程是否正確，另外為了配合FPGA之定點運算，亦做了幾項定點數測試，最後選擇Q19作為小數點解析度之格式，並以成對t-test檢定三者之辨識率以檢測定點數所造成的影響，結果顯示toolbox與Matlab類神經程式並沒有差異(P = 0.574 > 0.05)；而toolbox與Q19定點運算以及Matlab類神經程式與Q19定點運算則均有明顯差異(P值分別為0.00944及 0.04137)。FPGA完成後，以9位受測者之手部表面肌電訊號進行FPGA效能測試，同時利用成對t-test比較toolbox、Matlab神經網路與FPGA之辨識結果是否有差異，Matlab類神經程式與FPGA晶片之辨識結果具有明顯差異，P為0.002 (P<0.05)；toolbox 與FPGA晶片也具有差異，P為0.000035(P<0.05)。9位受測者中FPGA最高及最低辨識率分別為98.18％及83.64％(平均91.92±4.82％)。收斂速度方面，為了搭配DSP時脈，採用40MHZ作為系統測試時脈。其中最快及最慢之收斂速度分別為2.23秒及7.38秒，平均收斂速度為3.81±1.57秒。同時，最後晶片測試中，FPGA硬體資源使用仍有很大空間，類神經網路之大小可以藉由擴大各記憶體的方式再予以擴充，不需侷限在42*32*28之網路大小。

關鍵詞：表面肌電訊號(SEMG)、倒傳遞類神經網路、場效式可程式閘陣列(FPGA)

關鍵字

倒傳遞類神經網路 ； 場效式可程式閘陣列(FPGA) ； 表面肌電訊號(SEMG)

並列摘要

Abstract
The long term goal of this research is to develop a hand motion identification system using characteristics from the surface electromyogram (SEMG). The back-propagation neural network was selected as the center of the system. In the previous study, a wrist-band EMG acquisition system with seven active electrodes was completed. The characteristics form the acquired SEMGs were computed and inputted into the neural network for hand motion identification. Because the system is portable, using digital signal processor (DSP) to realize all the computation in software will consume too many resources and can’t achieve the requirement of real time. To design an application specific integrated circuit (ASIC) can not only help to increase the computation speed but also decrease the complexity of the program. However, it needs longer time to develop. In contrast, FPGA provides a transitional solution and it is easier to debug. Thus, in this study, it was use to develop a neural network chip with the capability of learning. The master-slave architecture was incorporated between DSP and FPGA chip.
First, in this study, a Matlab program was developed to test and verify the correctness of the neural network algorithm. By doing so, it will help to decrease the time in debugging. Only after the software test is successfully completed, the FPGA development and testing procedures will start. In the software testing, the Matlab program was compared with the neural network routine in the Matlab toolbox in order to verify the correctness of the program. Additionally, we tested the effect of fixed-point representation to match the FPGA’s fixed point calculation. At the end, the Q19 format was determined. The results of t-test show that there was no difference between Matlab toolbox and Matlab program (P=0.574>0.05). However, there were significant differences between Matlab toolbox and Q19 format and Matlab program and Q19 format. The p values were 0.00944 and 0.04137, respectively. The SEMGs from nine subjects were used to test the performance of FPGA. The results of t-test showed that there was difference between Matlab program and FPGA chip (p = 0.002 < 0.05). And there was difference between Matlab toolbox and FPGA chip (p = 0.000035 < 0.05). The best discrimination rate was 98.18% and the worst discrimination rate was 83.64%. The average discrimination rate was 91.92±4.82%. During the hardware test, in order to match the DSP clock frequency, we chose 40MHz for system clock frequency. The fastest convergence time for FPGA neural network training was 2.23 seconds and the worst convergence time was 7.38 seconds. The average convergence time is 3.81±1.57 seconds. Additionally, it was found that there were a lot of hardware resources still available in the FPGA during the final testing. Thus, this neural network can be easily expanded by increasing the memory that was used to store the input data and weights.

Keyword:
surface electromyogram (SEMG), back-propagation neural network, field programmable gate array (FPGA)

並列關鍵字

back-propagation neural network ； field programmable gate array (FPGA) ； surface electromyogram (SEMG)

參考文獻

[13] 田榮雯, “以FPGA實現倒傳遞類神經網路並應用於肌電圖分類”, 中原大學醫學醫學工程系碩士論文,2001

[17] 陳建宇, “多電極式手部動作辨識系統”, 中原大學醫學醫學工程系碩士論文,2001

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