與CMOS製程相容之奈米碳管場效電晶體氣體感測元件之研究

A Study of Carbon nanotube Field effect Transistor Gas Sensor compatible with CMOS

林良澤(Liang-Tse Lin)

指導教授 ： 黃榮堂

國立臺北科技大學/機電學院/機電整合研究所/碩士(2007年)

摘要

本研究將開發一與標準CMOS製程相容之奈米碳管場效電晶體作為氣體感測元件，由於奈米碳管目前生產所需溫度皆高於CMOS製程晶片之金屬所容許溫度，如以台灣積體電路製造公司 0.35μm 2P4M製程鋁合金最高容許溫度為380℃。因此，本研究以CMOS晶片最上層金屬（Metal 4）作為電極材料，並用陽極氧化與硝酸氧化方式使閘極表面生長一層超薄氧化鋁，並成功在CMOS晶片上以Lift-off沈積方式製作源極與汲極電極，再將半導體型單壁奈米碳管跨接於源極與汲極間，形成奈米碳管場效電晶體元件，經量測發現在施加源極與汲極偏壓1V下，操控閘極電壓-1.5V~+1.5V變化，其導通電流變化量約為1.5~4倍，而量測此時之閘極漏電流小於1×10-9A，約為導通電流之10-1~10-4倍不等，確認陽極氧化與硝酸氧化可使CMOS晶片之電極表面產生一氧化層。
本研究發現陽極氧化與硝酸氧化將在氧化鋁表面產生裂縫或孔洞，此缺陷將使得後續沈積金屬填充而與閘極金屬連通，而形成漏電路徑（Leakage path），且大面積的源極與汲極電極，將因為覆蓋氧化層面積增加因素，將導致漏電流發生機率提高。
本研究更證明利用利用介電泳力（Dielectrophoresis, DEP)操控奈米碳管時將因電場變化衝擊影響氧化鋁結構，進而使氧化鋁產生漏電路徑。因此，本研究提出一利用滴定法自然散佈方式組裝奈米碳管，經由量測結果顯示此奈米碳管場效電晶體導通電流結果可分為（1）閘極可操控性；（2）部分可操控性與（3）無導通電流等三種型式。由於以自然散佈方式無法操控奈米碳管方向與位置，以致於由奈米碳管堆疊網路所形成之導通路徑無法控制，當奈米碳管與金屬電極接觸點將產生蕭特基屏障（Schottky Barrier），若此導通路徑端點位於閘極電壓可操控範圍外時，將無法造成有效調整奈米碳管場效電晶體的導通電流，而當導通路徑位於閘極電壓可操控區域時將具有可操控性。
未來此感測元件可於奈米碳管表面進行改質，由於其閘極操控可調整感測器之感測靈敏度，將可提供未來作為生化感測元件之有效方法，並結合CMOS訊號處理電路達到實現可穿戴式（Wearable）單晶片（SoC）的目的。

關鍵字

奈米碳管 ； 奈米碳管場效電晶體 ； 低溫製程 ； 介電泳力 ； 互補式金屬-氧化層-半導體元件

並列摘要

In this thesis, we developed a CNTFETs device compatible with the TSMC CMOS process. The production temperature of the carbon nanotube is higher than the limitation of the CMOS . For example, the limitation of the CMOS chip made by for TSMC 0.35μm 2P4M is 380℃. Therefore, the metal 4 layer could be the electrode structure upon the CMOS chip and a ultra thin alumina layer would grow on the gate electrode surface by anodizing and nitric acid oxidation. The drain and source electrodes would be deposited on the CMOS chip by lift-off process and the s-SWNTs would connected with the drain and source electrode to form a CNTFETs.
Apply a bias voltage 1V on the drain and source, and a varied voltage from -1.5V to +1.5V on the gate, measure the conduction current (Ids) that increased from 1.5 to 4 times. The leakage current was less than 1 X10-9A and 10-2~ 10-4 times of the conduction current. The alumina layer made by anodizing and nitric acid oxidation on the aluminum of the CMOS chip could be confirmed.
There were cracks and holes on the alumina layer made by anodizing and nitric acid oxidation, and the leakage path will be formed after depositing Au on the alumina layer connected with the gate electrode. The probility of the leakage path would be increased while the deposited drain and source area increased.
After applying Dielectrophoresis AC on the electrodes to control carbon nanotube, the alumina layer would be damaged by the electric field impact and there would be a leakage current on the CNTFETs. Therefore, a droping method to distribute carbon nanotube on the electrodes was applied in the study. Measuring the properties of the CNTFETs and there are three results, gate voltage controllable, partial gate voltage controllable and no conduction current, in the CNTFETs. Because of the distributing carbon nanotube naturally on the COMS chip to connect the drain electrode and the source electrode, the location and direction of carbon nanotube could not be control. It means the conducting path formed by carbon nanotube network could not be controlled. While the contact area of the carbon nanotube and the conducting path is outside the gate voltage controllable area, the condutction current could not be controlled. Otherwise, the conduction current of the CNTFETs could be controlled by the gate voltage while there was a s-SWNT connected the drain and source upon the gate oxide layer

並列關鍵字

Carbon Nanotubes ； Carbon Nanotube Field-Effect Transistors ； Low-Temperature Fabrication ； Dielectrophoresis ； CMOS Integrated Devices

參考文獻

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