提高解碼效率與吞吐量之硬式決策停止策略渦輪解碼器設計

Enhancing Decoding Efficiency and Throughput of Hard Decision Stopping Criterion Method for Turbo Decoder Design

陳冠嘉(Kuan-Chia Chen)

指導教授 ： 李文達

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2011年)

https://doi.org/10.6841/NTUT.2011.00355

摘要

本論文提出以低延遲渦輪解碼器為基礎，且使用相位(Phase)方式來檢測的高解碼效率、高吞吐量之提前終止疊代渦輪碼解碼器積體電路設計。主要改善一般渦輪碼解碼器電路在解碼完成時無法自行停止，消耗過多功率的問題，來提升解碼效率，與提高吞吐量。以極低延遲的渦輪解碼器為架構，並輔以不同於一般的停止疊代演算法，我們使用相位估算的停止策略來減少疊代運算次數，以提高渦輪碼解碼器的效率，使它使用較少的解碼時間與功率消耗並可提高解碼器的吞吐量。而低延遲滑動視窗渦輪解碼器架構，可達到低延遲的效果，並且減少邏輯運算單元的數量，提升解碼器應用效率。綜合低延遲解碼器與相位估算停止策略，完成了一個高解碼效率與吞吐量之硬式決策停止策略渦輪解碼器。
最後，我們將所提出之「提高解碼效率與吞吐量之硬式決策停止策略渦輪解碼器」渦輪碼解碼器，以TSMC 0.18μm 1P6M製程之Cell-based流程來完成晶片的實現。其晶片面積大小約為1.6 x 1.6 mm^2，工作頻率為76.45MHz。

關鍵字

渦輪碼解碼器 ； 解碼效率 ； 停止策略 ； 低功率 ； 吞吐量

並列摘要

This thesis is based on low latency turbo decoder architecture with phase estimation stopping criterion method to create a high decoding efficiency and high throughput turbo decoder. Mainly to solve the problem that the turbo decoder can't stop iteration while decoding completes and it consumes too much power, so it can enhance decoding efficiency and throughput of turbo decoder. Based on very low latency turbo decoder architecture, we apply phase estimation to decrease the iteration, so it costs less power and enhances the efficiency of the decoder hardware and throughput. Also our low latency sliding windows of turbo decoder architecture can achieve low latency and reducing logic unit to enhance decoding efficiency. Based on the above, an enhancing decoding efficiency and throughput of hard decision stopping criterion method turbo decoder is proposed.
Finally, this enhancing decoding efficiency and throughput of hard decision stopping criterion method for turbo decoder has been designed with TSMC 0.18um 1P6m to accomplish. The chip size is 1.6 x 1.6 mm^2 and working frequency is 76.45MHz.

並列關鍵字

Turbo decoder ； Decoding efficiency ； Stopping Criterion ； Low Power ； Throughput

參考文獻

[15] T.M.N. Ngatched, F. Takawira, “Simple stopping criterion for turbo decoding,”

Turbo Decoder,” Master thesis, National Taipei University of Technology, Taipei,

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