低接線複雜度平行渦輪碼解碼器之超大型積體電路架構設計

VLSI Architecture Design of Low Complicated Parallel Turbo Decoder

盧冠穎(Kuan-Ying Lu)

指導教授 ： 李文達

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2009年)

https://doi.org/10.6841/NTUT.2009.00391

摘要

渦輪碼具有極佳的錯誤更正能力且效能十分接近仙農極限(Shannon’s limit)之優點，但由於渦輪碼必須經過重複的遞迴運算以及以硬體實現所額外付出的延遲時間，造成解碼時間較長與較低的產出速度。為此本論文藉由分析平行渦輪碼演算法來提出一種降低接線複雜度之平行渦輪解碼器晶片電路設計，在處理上將資料分配器中的多工器藉由使用限制分割交錯表的設計方法來降低多工器的使用。並在不損失太多的解碼效能下完成較少硬體接線的複雜度，以提供實現高階平行處理渦輪解碼器的使用者降低接線複雜度的設計方式。
　　我們將所提出之低接線複雜度平行渦輪碼解碼器，以Xilinx之Virtex-4系列FPGA進行實體驗證，並採用TSMC 0.18μm 1P6M CMOS製程，以Cell-based IC設計流程完成晶片設計。此晶片共使用178832 Gate counts，面積大小含I/O pad為4.014x4.014mm^2，工作頻率為42MHz。

關鍵字

渦輪碼解碼器 ； 平行處理渦輪解碼器

並列摘要

Excellent error correction capability and near Shannon limiting performance make turbo code to be the most important error correcting code recently. However, turbo decoder uses enormous calculations and iterations, which is difficult to be implemented and has a long decoding latency. In this thesis, we focus on parallel turbo decoder algorithms and develop a new low complicated VLSI design method for turbo decoder. With limited dividable interleaver, the number of routing multiplexers and routing complexity can be reduced efficiency. This proposed architecture can realize high order parallel turbo decoder with low complexity of multiplexer wire connecting.
To verify the proposed parallel turbo decoder, we have used the Xilinx Virtex-4 FPGA to emulate the hardware architecture, and we have designed this turbo decoder chip with TSMC 0.18μm 1P6M CMOS technology. This decoder chip uses 242,876 gate counts. Chip size including I/O pad is4.014x4.014mm^2,and operation frequency is 42M Hz .

並列關鍵字

Turbo decoder ； Parallel turbo decoder

參考文獻

[26] Ming-Chang Lee, Chip Design for a High Speed Turbo Decoder, Master thesis, National Taipei University of Technology, Taipei, Taiwan, July 2004.

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