結合渦輪碼UEP之H.264分層編解碼器晶片設計

A New VLSI Architecture of H.264 Layer Codec and UEP for Turbo Code

黃世鴻(Shih-Hung Huang)

指導教授 ： 李文達

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2006年)

摘要

H.264/AVC具有極佳的編碼壓縮效能，但高壓縮率的編碼技術，其對傳輸誤碼的要求更為嚴荷。為此本論文分析H.264/AVC碼流之重要性，且提出一種結合渦輪碼及用不均等錯誤保護方式來供H.264/AVC用之新型分層編解碼演算法。其中藉由渦輪碼提供不同之編碼碼率及解碼遞迴次數，對於H.264/AVC碼流中重要的部份給予比較高的錯誤保護，而不重要的部份給予比較低的錯誤保護，在本論文中提出四層不同層級，對應四種不同的錯誤保護，藉由渦輪碼具有極佳的錯誤更正能力且效能十分接近仙農極限之優點，可讓傳輸誤碼大為降低。此外在本論文中我們也分析比較未分層編碼搭配渦輪碼相等錯誤保護(EEP)與分層編碼搭配渦輪碼不均等錯誤保護(UEP)之效能。在節省頻寬架構裡，UEP1相較EEP1其頻寬可節省16.19%~19.56%，而消耗功率只增加分層編解碼之平均功率0.93mW、視訊PSNR只下降0.28db~0.39db。在節省功率架構裡，UEP2相較EEP2其消耗功率可節省約30.22%~34.02%，且視訊PSNR可提昇2.63db~2.93db，而頻寬需增加20.66%~25.72%。其中EEP1採用1/3碼率且四次遞迴，而UEP1採用1/3、1/3、1/2、1/2碼率，四、四、六、六遞迴次數，排列方式由重要性高至低，而EEP2採用1/2碼率且八次遞迴，UEP2採用1/3、1/3、1/2、1/2碼率，四、四、六、四遞迴次數，排列方式由重要性高至低。為了驗證架構的可行性，我們採用Xilinx Vertix-4 FPGA予以驗証。最後再以TSMC 0.18μm 1P6M CMOS製程來完成一個分層編碼器與分層解碼器的晶片佈局與驗證。

關鍵字

H.264 ； 分層編碼 ； 不均等錯誤保護

並列摘要

H.264/AVC has excellent compression performance for video code. However, the requirement of transmission error bits is stricter for high compression rate encoding technology. In this thesis, we analysis the significance of the H.264/AVC compressed bitstream and propose a new layer codec algorithm which combines UEP method with turbo code. Turbo code can provide various coding rate and iteration times, which gives higher error protection for the important parts of H.264/AVC compressed bitstream and lower error protection for the unimportant parts. In our design, we separate the H.264/AVC compressed bitstream into four different levels to provide four different error protection abilities. We also compare the performance of non-layered coding with turbo code equal error protection and layered coding with turbo code unequal error protection. Simulation results show that UEP1 with bandwidth-saving architecture can save 16.19%~19.56% bandwidth in comparisons with EEP1 and the power dissipation only increases 0.93mW, the video PSNR only decreases 0.28db~0.39db. In the power-saving architecture, UEP2 can save 30.22%~34.02% power dissipation in comparisons with EEP2 and the video PSNR increases 2.63db~2.93db, the bandwidth increases 20.66%~25.72%. For demonstrating this method, we use Xilinx Vertix-4 FPGA to test and verify the layered codec architecture. Finally, we have designed a layered encoder and layered decoder chips with TSMC 1P6M CMOS technology. These chips can operate up to 101.MHz and the chip area of layered encoder occupies 0.96 mm 0.96 mm, layered decoder occupies 1.13mm 1.13mm.

並列關鍵字

H.264 ； layered coding, turbo code ； unequal error protection

參考文獻

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