低延遲渦輪碼解碼器之超大型積體電路架構設計

本論文提出一個以低延遲解碼為訴求的渦輪碼解碼器之超大型積體電路架構設計。我們主要提出兩種方法來降低渦輪碼解碼器之解碼延遲，一是新型解碼相位重疊方法，藉由改善最大事後機率解碼器之滑動視窗解碼流程，以提高解碼器邏輯運算單元的硬體使用效率，可降低解碼延遲至0L視窗位置；另外，我們也提出新型同步式解碼架構，藉由改善解碼器之資料接收緩衝器，來達到低延遲的解碼效能。最後並整合此兩種低延遲解碼方法與架構，更進一步地降低解碼延遲時間。　　我們將所提出之低延遲渦輪碼解碼器，以Xilinx之Virtex-4系列FPGA進行實體驗證，並採用TSMC 0.18μm 1P6M CMOS製程完成晶片設計，此晶片共使用71488 Gate counts，面積大小含I/O pad為1.72 × 1.72mm2，功率消耗124.97mW，當工作頻率為83.33MHz，疊代次數為8次時，其資料吞吐量約為4.88Mbps。在不同的碼框長度下，相較於傳統的渦輪碼解碼器，解碼相位重疊式架構，可降低2.86% ~ 19.05%的解碼延遲時間。若再整合資料接收解碼同步架構，約可降低8.39% ~ 22.62%的解碼延遲時間。

關鍵字

渦輪碼解碼器；低延遲；超大型積體電路

並列摘要

In this thesis, we present two low latency decoding methods for VLSI Turbo decoder. In our design, we propose a novel sliding window operating flow, called Decoding Phase Overlapping method. It can improve the hardware efficiency and reduce the decoding delay of Turbo decoder. With this improved methodology, we have four decoding windows latency can be saved in comparison with traditional decoders. Besides, we also propose a novel Synchronous Decoding architecture, that modifies the data received buffer to reduce the decoding time. Finally we have integrated the two methods to save the decoding latency of Turbo decoder further. To verify the proposed low latency Turbo decoders, we have used the Xilinx Virtex-4 FPGA to emulate the hardware architectures, and we have designed this Turbo decoder chip with TSMC 0.18μm 1P6M CMOS technology. This decoder chip is 71488 gate counts. Chip size including I/O pad is 1.72×1.72mm2. Power consumption is 124.97mW. Experimental result shows that for different code size, the decoding phase overlapping method has 2.86% ~ 19.05% decoding time saved, and the synchronous decoding architecture integrated has 8.39% ~ 22.62% decoding time saved with 8 iteration times at 83.33MHz working frequency.

並列關鍵字

Turbo decoder ； Low latency ； VLSI

參考文獻

[24] Ming-Chang Lee, Chip design for a high speed turbo decoder, Master thesis, National Taipei University of Technology, Taipei, Taiwan, July 2004.

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國際替代計量

低延遲渦輪碼解碼器之超大型積體電路架構設計

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